Welcome to BasejumpDoc’s documentation!¶
bsg_dataflow¶
tag¶
bsg_1_to_n_tagged¶
Overview
This module is intended to take one input and send it to one of several channels according to tag.
Parameter
NAME DESCRIPTION DEFAULT num_out_p input and output data width -1 tag_width_lp input data width `BSG_SAFE_CLOG2(num_out_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock port RESET reset_i 1 reset port INPUT v_i width_p data input port tag_i tag_width_lp data input port ready_i num_out_p data input port OUTPUT yumi_o 1 data output port v_o num_out_p data output port Assertion
None
Details & Circuit structure
bsg_1_to_n_tagged_fifo¶
Overview
This module implements a FIFO that takes in a multiplexed stream on one end, and provides demultiplexed access on the other.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” num_out_p input data width -1 els_p input data width “inv” unbuffered_mask_p input data width 0 use_pseudo_large_fifo_p input data width 0 tag_width_lp input data width `BSG_SAFE_CLOG2(num_out_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock port RESET reset_i 1 reset port INPUT v_i 1 data input port tag_i tag_width_lp data input port data_i width_p data input port yumi_i num_out_p data input port OUTPUT yumi_o 1 data output port v_o num_out_p data output port data_o num_out_p*width_p data output port Assertion
None
Details & Circuit structure
bsg_1_to_n_tagged_fifo_shared¶
Overview
This module implements a FIFO that takes in a multiplexed stream on one end, and provides demultiplexed access on the other.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” num_out_p input data width -1 els_p input data width “inv” unbuffered_mask_p input data width 0 use_pseudo_large_fifo_p input data width 0 tag_width_lp input data width `BSG_SAFE_CLOG2(num_out_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock port RESET reset_i 1 reset port INPUT v_i 1 data input port tag_i tag_width_lp data input port data_i width_p data input port yumi_i num_out_p data input port OUTPUT yumi_o 1 data output port v_o num_out_p data output port data_o num_out_p*width_p data output port Assertion
None
Details & Circuit structure
Decode Releted Unit¶
bsg_8b10b_decode_comb¶
Overview
This module is byte oriented DC balanced 8B/10B block transfer decoder.
Parameter
None
Port
TYPE NAME WIDTH DESCRIPTION INPUT data_i 10 data input port rd_i 1 data input port OUTPUT data_o 8 data output port k_o 1 data output port rd_o 1 data output port data_err_o 1 data output port rd_err_o 1 data output port Assertion
None
Details & Circuit structure
bsg_8b10b_encode_comb¶
Overview
This module is byte oriented DC balanced 8B/10B block transfer encoder.
Parameter
None
Port
TYPE NAME WIDTH DESCRIPTION INPUT data_i 8 data input port k_i 1 data input port rd_i 1 data input port OUTPUT data_o 10 data output port rd_o 1 data output port kerr_o 1 data output port Assertion
None
Details & Circuit structure
bsg_8b10b_shift_decoder¶
Overview
This module is byte oriented DC balanced 8B/10B block transfer decoder with shift register.
Parameter
None
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clock 1 clock input port INPUT data_i 1 data input port OUTPUT data_o 8 data output port k_o 1 data output port v_o 1 data output port frame_align_o 1 data output port Assertion
None
Details & Circuit structure
Channel Narrow Unit¶
bsg_channel_narrow¶
Overview
This module takes output of a previous module and sends this data in smaller number of bits by receiving deque from next module.
Parameter
NAME DESCRIPTION DEFAULT width_in_p input data width -1 width_out_p output data width -1 lsb_to_msb_p select signal 1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clock 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_in_p data input port deque_i 1 data input port OUTPUT deque_o 1 data output port data_o 1width_out_p data output port Assertion
None
Details & Circuit structure
bsg_channel_narrow¶
Overview
This module takes output of a previous module and sends this data in smaller number of bits by receiving deque from next module.
Parameter
NAME DESCRIPTION DEFAULT width_in_p input data width -1 width_out_p output data width -1 lsb_to_msb_p select signal 1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clock 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_in_p data input port deque_i 1 data input port OUTPUT deque_o 1 data output port data_o 1width_out_p data output port Assertion
None
Details & Circuit structure
Channel Tunnel Releted Unit¶
bsg_channel_tunnel¶
Overview
This module allows you to multiplex multiple streams over a shared interconnect without having deadlock occur because of stream interleaving.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width 1 num_in_p input and output data width “inv” remote_credits_p input data width “inv” use_pseudo_large_fifo_p input data width 0 lg_remote_credits_lp internal signal width $clog2(remote_credits_p+1) lg_credit_decimation_p input data width `BSG_MIN(lg_remote_credits_lp,4) tag_width_lp input data width $clog2(num_in_p+1) tagged_width_lp input data width tag_width_lp + width_p
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clock 1 clock input port RESET reset_i 1 reset input port INPUT multi_data_i tagged_width_lp data input port multi_v_i 1 data input port multi_yumi_i 1 data input port data_i num_in_p*width_p data input port v_i num_in_p data input port yumi_i num_in_p data input port OUTPUT multi_yumi_o 1 data output port multi_data_o tagged_width_lp data output port multi_v_o 1 data output port yumi_o num_in_p data output port data_o num_in_p*width_p data output port v_o num_in_p data output port Assertion
None
Details & Circuit structure
bsg_channel_tunnel_in¶
Overview
This module takes N channels and tunnels them, with credit flow control.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 num_in_p input and output data width “inv” remote_credits_p input data width “inv” use_pseudo_large_fifo_p input data width 0 lg_remote_credits_lp internal signal width $clog2(remote_credits_p+1) lg_credit_decimation_p input data width 4 tag_width_lp input data width $clog2(num_in_p+1) tagged_width_lp input data width tag_width_lp+width_p
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clock 1 clock input port RESET reset_i 1 reset input port INPUT data_i tagged_width_lp data input port v_i 1 data input port yumi_i num_in_p data input port OUTPUT yumi_o 1 data output port data_o num_in_p*width_p data output port v_o num_in_p data output port credit_local_return_data_o num_in_p*lg_remote_credits_lp data output port credit_local_return_v_o num_in_p*width_p data output port Assertion
None
Details & Circuit structure
bsg_channel_tunnel_out¶
Overview
This module takes N channels and tunnels them, with credit flow control.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 num_in_p input and output data width “inv” remote_credits_p input data width “inv” lg_remote_credits_lp internal signal width $clog2(remote_credits_p+1) lg_credit_decimation_p input data width 4 tag_width_lp input data width $clog2(num_in_p+1) tagged_width_lp input data width tag_width_lp+width_p
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clock 1 clock input port RESET reset_i 1 reset input port INPUT data_i num_in_p*width_p data input port v_i num_in_p data input port yumi_i 1 data input port credit_local_return_data_i 1 data output port credit_local_return_v_i 1 data output port credit_remote_return_data_i 1 data output port OUTPUT yumi_o num_in_p data output port data_o tagged_width_lp data output port v_o 1 data output port credit_remote_return_yumi_o 1 data output port Assertion
None
Details & Circuit structure
bsg_channel_tunnel_wormhole¶
Overview
This module is a special version bsg_channel_tunnel that accepts wormhole packet.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” x_cord_width_p data width “inv” y_cord_width_p data width “inv” len_width_p length width “inv” reserved_width_p data width “inv” num_in_p total number of inputs multiplexed “inv” remote_credits_p max number of wormhole packets buffer can store “inv” max_payload_flits_p max possible “wormhole packet payload length” setting “inv” lg_credit_decimation_p how often does channel tunnel return credits to sender `BSG_MIN($clog2(remote_credits_p+1),4) use_pseudo_large_fifo_p use pseudo large fifo when read / write utilization is less than 50% 1 bsg_ready_and_link_sif_width_lp local parameters `bsg_ready_and_link_sif_width(width_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clock 1 clock input port RESET reset_i 1 reset input port INPUT multi_data_i width_p data input port multi_v_i 1 data input port multi_yumi_i 1 data input port link_i num_in_p*bsg_ready_and_link_sif_width_lp data input port OUTPUT multi_ready_o 1 data output port multi_data_o width_p data output port multi_v_o 1 data output port link_o num_in_p*bsg_ready_and_link_sif_width_lp data output port Assertion
None
Details & Circuit structure
Compare Swap Releted Unit¶
bsg_compare_and_swap¶
Overview
This module compare two values and swap them if they are not in order.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” t_p data range `BSG_SAFE_CLOG2(num_out_p) b_p data range `BSG_SAFE_CLOG2(num_out_p) cond_swap_on_equal_p select signal `BSG_SAFE_CLOG2(num_out_p)
Port
TYPE NAME WIDTH DESCRIPTION INPUT data_i 2*width_p data input port swap_on_equal_i 1 data input port OUTPUT data_o 2*width_p data output port swapped_o 1 data output port Assertion
None
Details & Circuit structure
Counter Releted Unit¶
bsg_credit_to_token¶
Overview
This module is a counter for credits, that every decimation_p credits it would assert token_o signal once.
Parameter
NAME DESCRIPTION DEFAULT decimation_p signal width -1 max_val_p signal width -1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT credit_i 1 data input port ready_i 1 data input port OUTPUT token_o 1 data output port Assertion
None
Details & Circuit structure
RAM Releted Unit¶
bsg_fifo_1r1w_large¶
Overview
This implementation is specifically intended for processes where 1RW rams are much cheaper than 1R1W rams.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p internal signal width -1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port v_i 1 data input port yumi_i 1 data input port OUTPUT ready_o 1 data output port v_o 1 data output port data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_fifo_1r1w_large_banked¶
Overview
This implementation using two banks is specifically intended for processes where 1RW rams are much cheaper than 1R1W rams.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p internal signal width -1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port v_i 1 data input port yumi_i 1 data input port OUTPUT ready_o 1 data output port v_o 1 data output port data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_fifo_1r1w_narrowed¶
Overview
This module is a small fifo which has a bsg_channel_narrow on its output, that would send out each data in several steps based on the input and output width.
Parameter
NAME DESCRIPTION DEFAULT width_p input data width -1 els_p internal signal width -1 width_out_p output data width -1 lsb_to_msb_p select signal -1 ready_THEN_valid_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port v_i 1 data input port yumi_i 1 data input port OUTPUT ready_o 1 data output port v_o 1 data output port data_o width_out_p data output port Assertion
None
Details & Circuit structure
bsg_fifo_1r1w_pseudo_large¶
Overview
This fifo looks like a 1R1W fifo but actually is implemented with a 1RW FIFO for the bulk of its storage, and has a small 1R1W FIFO to help decouple reads and writes that may conflict.
Parameter
NAME DESCRIPTION DEFAULT width_p input data width -1 els_p internal signal width -1 early_yumi_p select signal 1 verbose_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port v_i 1 data input port yumi_i 1 data input port OUTPUT ready_o 1 data output port v_o 1 data output port data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_fifo_1r1w_small¶
Overview
This module implements a FIFO with 1 read and 1 write and can use different memory implementations.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p internal signal width -1 harden_p use harden IP or not 0 ready_THEN_valid_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port v_i 1 data input port yumi_i 1 data input port OUTPUT ready_o 1 data output port v_o 1 data output port data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_fifo_1r1w_small_credit_on_input¶
Overview
This module converts between the valid-credit (input) and valid-ready (output) handshakes, by using a fifo to keep the data.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p internal signal width -1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port v_i 1 data input port yumi_i 1 data input port OUTPUT credit_o 1 data output port v_o 1 data output port data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_fifo_1r1w_small_hardened¶
Overview
This module is a FIFO with 1 read and 1 write,used for smaller FIFOs.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p internal signal width -1 ready_THEN_valid_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port v_i 1 data input port yumi_i 1 data input port OUTPUT ready_o 1 data output port v_o 1 data output port data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_fifo_1r1w_small_unhardened¶
Overview
This module is a FIFO with 1 read and 1 write,using 1-write 1-async-read resgister file implementation.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p internal signal width -1 ready_THEN_valid_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port v_i 1 data input port yumi_i 1 data input port OUTPUT ready_o 1 data output port v_o 1 data output port data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_fifo_1rw_large¶
Overview
This module is a FIFO with only one read or write port, using a 1RW synchronous read ram.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p internal signal width -1 verbose_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port v_i 1 data input port enq_not_deq_i 1 data input port OUTPUT full_o 1 data output port empty_o 1 data output port data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_fifo_bypass¶
Overview
This module is a FIFO bypass circuit.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” ready_THEN_valid_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT data_i width_p data input port v_i 1 data input port yumi_i 1 data input port fifo_ready_i width_p data input port fifo_data_i width_p data input port fifo_v_i 1 data input port OUTPUT ready_o 1 data output port data_o width_p data output port v_o 1 data output port fifo_data_o width_p data output port fifo_v_o 1 data output port fifo_yumi_o 1 data output port Assertion
None
Details & Circuit structure
bsg_fifo_reorder¶
Overview
This module is a reordering circuit for FIFO.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” els_p Internal signal range “inv” lg_els_lp input and output data width `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT fifo_alloc_yumi_i 1 data input port write_v_i 1 data input port write_id_i 1 data input port write_data_i width_p data input port fifo_deq_yumi_i 1 data input port OUTPUT fifo_alloc_v_o 1 data output port fifo_alloc_id_o lg_els_lp data output port fifo_deq_v_o 1 data output port fifo_deq_data_o width_p data output port empty_o 1 data output port Assertion
None
Details & Circuit structure
bsg_fifo_shift_datapath¶
Overview
This module creates an array of shift registers, with independently controlled three input muxes.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” els_p input data width “inv” default_p default initial value { (width_p) {1’b0} }
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port INPUT data_i width_p data input port sel_i els_p*2 data input port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_fifo_tracker¶
Overview
This module returns whether FIFO is empty or full.
Parameter
NAME DESCRIPTION DEFAULT els_p input and output data width -1 ptr_width_lp input and output data width `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT enq_i 1 data input port deq_i 1 data input port OUTPUT wptr_r_o ptr_width_lp data output port rptr_r_o ptr_width_lp data output port rptr_n_o ptr_width_lp data output port full_o 1 data output port empty_o 1 data output port Assertion
None
Details & Circuit structure
bsg_flatten_2D_array¶
Overview
This module converts a two-dimensional array to a one-dimensional array.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 items_p input and output data width -1
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p*items_p data input port OUTPUT o width_p*items_p data output port Assertion
None
Details & Circuit structure
bsg_flow_convert¶
Overview
This module converts between the various link-level flow-control protocols.
Parameter
NAME DESCRIPTION DEFAULT send_v_and_ready_p input data width 0 send_v_then_yumi_p select signal 0 send_ready_then_v_p select signal 0 send_retry_then_v_p select signal 0 send_v_and_retry_p select signal 0 recv_v_and_ready_p select signal 0 recv_v_then_yumi_p select signal 0 recv_ready_then_v_p select signal 0 recv_v_and_retry_p select signal 0 recv_v_then_retry_p select signal 0 width_p input and output data width 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT v_i width_p data input port fc_i width_p data input port OUTPUT fc_o width_p data output port v_o width_p data output port Assertion
None
Details & Circuit structure
bsg_flow_counter¶
Overview
This module counts the number of free elements or number of existing elements in the connected module.
Parameter
NAME DESCRIPTION DEFAULT els_p output data width -1 count_free_p select signal 0 ready_THEN_valid_p select signal 0 ptr_width_lp output data width `BSG_WIDTH(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT v_i 1 data input port ready_i 1 data input port yumi_i 1 data input port OUTPUT count_o ptr_width_lp data output port Assertion
None
Details & Circuit structure
bsg_make_2D_array¶
Overview
This module creates a two-dimensional array.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 items_p input and output data width -1
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p*items_p data input port OUTPUT o width_p*items_p data output port Assertion
None
Details & Circuit structure
bsg_one_fifo¶
Overview
This module is used to pipeline links and convert interfaces from valid/ready to valid->yumi.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port v_i 1 data input port yumi_i 1 data input port OUTPUT ready_o 1 data output port v_o 1 data output port data_o ptr_width_lp data output port Assertion
None
Details & Circuit structure
parallel in serial out¶
bsg_parallel_in_serial_out¶
Overview
This module takes in a multi-word data and serializes it to a single word output.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 hi_to_lo_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i els_p*width_p data input port valid_i 1 data input port yumi_i 1 data input port OUTPUT ready_o 1 data output port valid_o 1 data output port data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_parallel_in_serial_out_dynamic¶
Overview
This module takes in a multi-word data and serializes it to a single word output.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” max_els_p input data width “inv” lg_max_els_lp input data width `BSG_SAFE_CLOG2(max_els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT v_i 1 data input port len_i lg_max_els_lp data input port data_i max_els_p*width_p data input port yumi_i 1 data input port OUTPUT ready_o 1 data output port v_o 1 data output port len_v_o 1 data output port data_o width_p data output port Assertion
None
Details & Circuit structure
selector¶
bsg_permute_box¶
Overview
This module selects the input signal and outputs it.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” items_p input and output data width “inv” lg_items_lp input data width $bits(items_p)
Port
TYPE NAME WIDTH DESCRIPTION INPUT data_i width_p*items_p data input port select_i lg_items_lp*items_p data input port OUTPUT data_o width_p*items_p data output port Assertion
None
Details & Circuit structure
converter¶
bsg_ready_to_credit_flow_converter¶
Overview
This module converts between the valid-ready (input) and valid-credit (output) handshakes, by keeping the count of available credits.
Parameter
NAME DESCRIPTION DEFAULT credit_initial_p input and output data width -1 credit_max_val_p input data width -1 decimation_p select signal 1 ptr_width_lp internal signal bit width `BSG_WIDTH(credit_max_val_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT v_i 1 data input port credit_i 1 data input port OUTPUT ready_o 1 data output port v_o 1 data output port Assertion
None
Details & Circuit structure
bsg_relay_fifo¶
Overview
This module converts between the valid-ready (input) and valid-credit (output) handshakes, by keeping the count of available credits.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port v_i 1 data input port ready_i 1 data input port OUTPUT ready_o 1 data output port v_o 1 data output port data_o width_p data output port Assertion
None
Details & Circuit structure
Round Robin Releted Unit¶
bsg_round_robin_1_to_n¶
Overview
This module is intended to take one input and send it to one of several channels in round robin order.
Parameter
NAME DESCRIPTION DEFAULT width_p useless “inv” num_out_p input and output data width 2
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT valid_i 1 data input port ready_i num_out_p data input port OUTPUT ready_o 1 data output port valid_o num_out_p data output port Assertion
None
Details & Circuit structure
bsg_round_robin_2_to_2¶
Overview
This module is intended for round robining on the input to a pair of fifos.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p*2 data input port v_i 2 data input port ready_i 2 data input port OUTPUT ready_o 2 data output port data_o width_p*2 data output port v_o 2 data output port Assertion
None
Details & Circuit structure
bsg_rr_f2f_input¶
Overview
This module is intended for round robining on the input to a pair of fifos.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p*2 data input port v_i 2 data input port ready_i 2 data input port OUTPUT ready_o 2 data output port data_o width_p*2 data output port v_o 2 data output port Assertion
None
Details & Circuit structure
bsg_round_robin_n_to_1¶
Overview
This module is intended to merge the outputs of several fifos together to act as one.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 num_in_p input and output data width -1 strict_p select signal “inv” tag_width_lp output data width `BSG_SAFE_CLOG2(num_in_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i num_in_p*width_p data input port v_i num_in_p data input port yumi_i 1 data input port OUTPUT yumi_o num_in_p data output port v_o 1 data output port data_o width_p data output port tag_o tag_width_lp data output port Assertion
None
Details & Circuit structure
sbox¶
bsg_sbox¶
Overview
This module concentrates working channel signals to reduce the complexity of downstream logic.
Parameter
NAME DESCRIPTION DEFAULT num_channels_p input and output data width “inv” channel_width_p input and output data width “inv” pipeline_indir_p select signal “inv” pipeline_outdir_p select signal 0 one_hot_p select signal 1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT calibration_done_i 1 data input port channel_active_i num_channels_p data input port in_v_i num_channels_p data input port in_data_i channel_width_p*num_channels_p data input port out_me_v_i num_in_p*width_p data input port out_me_data_i num_in_p data input port out_me_ready_i 1 data input port in_yumi_i 1 data input port OUTPUT in_yumi_o num_channels_p data output port in_v_o num_channels_p data output port in_data_o channel_width_p*num_channels_p data output port out_me_ready_o num_channels_p data output port out_me_v_o num_channels_p data output port out_me_data_o channel_width_p*num_channels_p data output port Assertion
None
Details & Circuit structure
bsg_sbox_ctrl_concentrate¶
Overview
This module generates permutation vectors that perform concentration (fwd) and deconcentration (bkwd).
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 lg_width_p output data width -1
Port
TYPE NAME WIDTH DESCRIPTION INPUT vec_i width_p data input port OUTPUT fwd_perm_o lg_width_p*width_p data output port fwd_valid_o width_p data output port bkwd_perm_o lg_width_p*width_p data output port Assertion
None
Details & Circuit structure
Vectors Releted Unit¶
bsg_scatter_gather¶
Overview
This module generates permutation vectors that perform concentration (fwd) and deconcentration (bkwd).
Parameter
NAME DESCRIPTION DEFAULT vec_size_lp input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT vec_i width_p data input port OUTPUT fwd_o lg_width_p*width_p data output port fwd_datapath_o width_p data output port bk_o lg_width_p*width_p data output port bk_datapath_o lg_width_p*width_p data output port Assertion
None
Details & Circuit structure
data structure¶
bsg_serial_in_parallel_out¶
Overview
This module is a data structure that takes one word per cycle and allows more than one word per cycle to exit and the number of words extracted can vary dynamically.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p internal initial signal bit width -1 out_els_p input and output data width els_p
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT valid_i 1 data input port data_i width_p data input port yumi_cnt_i $clog2(out_els_p+1) data input port OUTPUT ready_o 1 data output port valid_o out_els_p data output port data_o out_els_p*width_p data output port Assertion
None
Details & Circuit structure
bsg_serial_in_parallel_out_dynamic¶
Overview
This module is a data structure that takes one word per cycle and allows more than one word per cycle to exit and the number of words extracted can vary dynamically.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” max_els_p internal initial signal bit width “inv” lg_max_els_lp input and output data width `BSG_SAFE_CLOG2(max_els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT v_i 1 data input port len_i width_p data input port data_i $clog2(out_els_p+1) data input port yumi_i 1 data input port OUTPUT ready_o 1 data output port len_ready_o 1 data output port v_o 1 data output port data_o max_els_p*width_p data output port Assertion
None
Details & Circuit structure
bsg_serial_in_parallel_out_full¶
Overview
This module is a simpler version of bsg_serial_in_parallel_out.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” els_p output data width “inv” hi_to_lo_p select signal 0 use_minimal_buffering_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT v_i 1 data input port data_i width_p data input port yumi_i 1 data input port OUTPUT ready_o 1 data output port data_o els_p*width_p data output port v_o 1 data output port Assertion
None
Details & Circuit structure
Shift Register Releted Unit¶
bsg_shift_reg¶
Overview
This module implements a shift register of fixed latency.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” stages_p internal initial signal bit width “inv”
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT valid_i 1 data input port data_i width_p data input port OUTPUT valid_o 1 data output port data_o width_p data output port Assertion
None
Details & Circuit structure
Sort Network Releted Unit¶
bsg_sort_4¶
Overview
This module is a sorting network implementation.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” items_p input and output data width 4 t_p inclusive range of bits width_p-1 b_p inclusive range of bits 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p*items_p data input port OUTPUT o width_p*items_p data output port Assertion
None
Details & Circuit structure
bsg_sort_stable¶
Overview
This module implements a stable 4-item sort.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” items_p input and output data width 4 t_p inclusive range of bits width_p-1 b_p inclusive range of bits 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p*items_p data input port OUTPUT o width_p*items_p data output port Assertion
None
Details & Circuit structure
two buncher¶
bsg_two_buncher¶
Overview
This module takes an incoming stream of words. if the output is read every cycle, the data passes straight through without latency. if the output is not read, then one element is buffered internally and either one or two elements may be pulled out on the next cycle.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i 1 data input port v_i width_p data input port ready_i width_p data input port OUTPUT ready_o 1 data output port data_o 2*width_p data output port v_o 2 data output port Assertion
None
Details & Circuit structure
Two FIFO¶
bsg_two_fifo¶
Overview
This module implements two element FIFO.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” verbose_p select signal 0 allow_enq_deq_on_full_p select signal 0 ready_THEN_valid_p select signal allow_enq_deq_on_full_p
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT v_i 1 data input port yumi_i 1 data input port OUTPUT ready_o 1 data output port data_o width_p data output port v_o 1 data output port Assertion
None
Details & Circuit structure
bsg_mem¶
CAM Releted Unit¶
bsg_cam_1r1w¶
Overview
This is an asynchronous read 1r1w content addressable memory module.
Parameter
NAME DESCRIPTION DEFAULT els_p internal signal bit width “inv” tag_width_p input data width “inv” data_width_p input and output data width “inv” repl_scheme_p select signal “lru”
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_nuke_i 1 data input port w_tag_i tag_width_p data input port w_data_i data_width_p data input port r_v_i 1 data input port r_tag_i tag_width_p data input port OUTPUT r_data_o data_width_p data output port r_v_o 1 data output port Assertion
None
Details & Circuit structure
bsg_cam_1r1w_replacement¶
Overview
This module maintains the replacement policy for an array of elements.
Parameter
NAME DESCRIPTION DEFAULT els_p internal signal bit width 2 scheme_p select signal “lru”
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT read_v_i els_p data input port alloc_v_i 1 data input port alloc_empty_i els_p data input port OUTPUT alloc_v_o els_p data output port Assertion
assert (scheme_p == “lru”) else $error(“Only LRU scheme is currently supported”);
Details & Circuit structure
bsg_cam_1r1w_sync¶
Overview
This is synchnronous read 1r1w content addressable memory module.
Parameter
NAME DESCRIPTION DEFAULT els_p internal signal bit width “inv” tag_width_p input data width “lru” data_width_p input and output data width 2 repl_scheme_p select signal “lru”
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_nuke_i 1 data input port w_tag_i tag_width_p data input port w_data_i data_width_p data input port r_v_i 1 data input port r_tag_i tag_width_p data input port OUTPUT r_data_o data_width_p data output port r_v_o 1 data output port Assertion
None
Details & Circuit structure
bsg_cam_1r1w_sync_unmanaged¶
Overview
This is synchnronous read 1r1w content addressable memory module,and each entry has a tag and a data associated with it, and can be independently cleared and set.
Parameter
NAME DESCRIPTION DEFAULT els_p input and output data width “inv” tag_width_p input data width “inv” data_width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i els_p data input port w_set_not_clear_i 1 data input port w_tag_i tag_width_p data input port w_data_i data_width_p data input port r_v_i 1 data input port r_tag_i tag_width_p data input port OUTPUT r_data_o data_width_p data output port r_v_o 1 data output port Assertion
None
Details & Circuit structure
bsg_cam_1r1w_tag_array¶
Overview
This module is made for use in bsg_cams, managing the valids and tags for each entry.
Parameter
NAME DESCRIPTION DEFAULT width_p input data width “inv” els_p input and output data width “inv” multiple_entries_p assert signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i els_p data input port w_set_not_clear_i 1 data input port w_tag_i tag_width_p data input port w_data_i data_width_p data input port r_v_i 1 data input port r_tag_i tag_width_p data input port OUTPUT w_empty_o els_p data output port r_match_o els_p data output port Assertion
assert(multiple_entries_p || reset_i || $countones(r_match_o) <= 1);
Details & Circuit structure
bsg_cam_1r1w_unmanaged¶
Overview
This is an asynchronous read 1r1w content addressable memory module, and Each entry has a tag and a data associated with it, and can be independently cleared and set.
Parameter
NAME DESCRIPTION DEFAULT els_p input and output data width “inv” tag_width_p input data width “inv” data_width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i els_p data input port w_set_not_clear_i 1 data input port w_tag_i tag_width_p data input port w_data_i data_width_p data input port r_v_i 1 data input port r_tag_i tag_width_p data input port OUTPUT w_empty_o els_p data output port r_data_o data_width_p data output port r_v_o els_p data output port Assertion
None
Details & Circuit structure
Asynchronous Mem Releted Unit¶
bsg_mem_1r1w¶
Overview
This module is 1 read-port and 1 write-port ram, and reads are asynchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p internal signal bit width -1 read_write_same_addr_p none 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) harden_p use harden IP or not 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK w_clk_i 1 clock input port RESET w_reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r_v_i 1 data input port r_addr_i addr_width_lp data input port OUTPUT r_data_o width_p data output port Assertion
assert ((w_reset_i === ‘X) || (w_reset_i === 1’b1) || (w_addr_i < els_p)); assert ((w_reset_i === ‘X) || (w_reset_i === 1’b1) || !(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p));
Details & Circuit structure
bsg_mem_1r1w_one_hot¶
Overview
This module is 1 read-port and 1 write-port ram with a onehot address scheme.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK w_clk_i 1 clock input port RESET w_reset_i 1 reset input port INPUT w_v_i els_p data input port w_data_i width_p data input port r_v_i els_p data input port OUTPUT r_data_o width_p data output port Assertion
assert ((w_reset_i === ‘X) || (w_reset_i === 1’b1) || $countones(w_v_i) <= 1); assert ((w_reset_i === ‘X) || (w_reset_i === 1’b1) || $countones(r_v_i) <= 1);
Details & Circuit structure
bsg_mem_1r1w_synth¶
Overview
This module is 1 read-port, 1 write-port ram for synthesizable internal version, and reads are asynchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 read_write_same_addr_p None 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) harden_p use harden IP or not 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK w_clk_i 1 clock input port RESET w_reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i w_data_i data input port r_v_i 1 data input port r_addr_i addr_width_lp data input port OUTPUT r_data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_2r1w¶
Overview
This module is a 2 read-port and 1 write-port ram, and reads are asynchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p select signal -1 read_write_same_addr_p None 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK w_clk_i 1 clock input port RESET w_reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r0_v_i 1 data input port r0_addr_i addr_width_lp data input port r1_v_i 1 data input port r1_addr_i addr_width_lp data input port OUTPUT r0_data_o width_p data output port r1_data_o width_p data output port Assertion
assert (w_addr_i < els_p) assert (!(r0_addr_i == w_addr_i && w_v_i && r0_v_i && !read_write_same_addr_p)) assert (!(r1_addr_i == w_addr_i && w_v_i && r1_v_i && !read_write_same_addr_p))
Details & Circuit structure
bsg_mem_2r1w_synth¶
Overview
This module is a 2 read-port and 1 write-port ram, and reads are asynchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p mem dimensions -1 read_write_same_addr_p None 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK w_clk_i 1 clock input port RESET w_reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r0_v_i 1 data input port r0_addr_i addr_width_lp data input port r1_v_i 1 data input port r1_addr_i addr_width_lp data input port OUTPUT r0_data_o width_p data output port r1_data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_3r1w¶
Overview
This module is a 3 read-port, 1 write-port ram, and reads are asynchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p mem dimensions -1 read_write_same_addr_p None 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK w_clk_i 1 clock input port RESET w_reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r0_v_i 1 data input port r0_addr_i addr_width_lp data input port r1_v_i 1 data input port r1_addr_i addr_width_lp data input port r2_v_i 1 data input port r2_addr_i addr_width_lp data input port OUTPUT r0_data_o width_p data output port r1_data_o width_p data output port r1_data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_3r1w_synth¶
Overview
This module is a 3 read-port, 1 write-port ram, and reads are asynchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p mem dimensions -1 read_write_same_addr_p None 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r0_v_i 1 data input port r0_addr_i addr_width_lp data input port r1_v_i 1 data input port r1_addr_i addr_width_lp data input port r2_v_i 1 data input port r2_addr_i addr_width_lp data input port OUTPUT r0_data_o width_p data output port r1_data_o width_p data output port r2_data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_multiport¶
Overview
This module is a N read-port and M write-port ram, and reads are asynchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p mem dimensions -1 read_write_same_addr_p assertion signal 0 write_write_same_addr_p assertion signal 0 read_ports_p input and output data width “inv” write_ports_p input data width “inv” addr_width_lp input data width `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK w_clk_i 1 clock input port RESET w_reset_i 1 reset input port INPUT w_v_i write_ports_p data input port w_addr_i write_ports_p*addr_width_lp data input port w_data_i write_ports_p*width_p data input port r_v_i read_ports_p data input port r_addr_i read_ports_p*addr_width_lp data input port OUTPUT r0_data_o read_ports_p*width_p data output port Assertion
assert (w_addr_i[i] < els_p); assert (~(w_addr_i[i] == r_addr_i[j] && w_v_i[i] && r_v_i[j] && !read_write_same_addr_p)); assert (~(w_addr_i[i] == w_addr_i[j] && w_v_i[i] && w_v_i[j] && !write_write_same_addr_p));
Details & Circuit structure
Synchronous Mem Releted Unit¶
bsg_mem_1r1w_sync¶
Overview
This module is 1 read-port and 1 write-port ram, and reads are synchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 read_write_same_addr_p input data width 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) harden_p use harden IP or not 0 disable_collision_warning_p detection signal 1 enable_clock_gating_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r_v_i 1 data input port r_addr_i addr_width_lp data input port OUTPUT r_data_o width_p data output port Assertion
assert ((reset_i === ‘X) || (reset_i === 1’b1) || (w_addr_i < els_p)); assert ((reset_i === ‘X) || (reset_i === 1’b1) || ~(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p && !disable_collision_warning_p));
Details & Circuit structure
bsg_mem_1r1w_sync_mask_write_bit¶
Overview
This module is 1 read-port and 1 write-port ram with mask, and reads are synchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 read_write_same_addr_p input data width 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) harden_p use harden IP or not 0 disable_collision_warning_p detection signal 1 enable_clock_gating_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_mask_i width_p data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r_v_i 1 data input port r_addr_i addr_width_lp data input port OUTPUT r_data_o width_p data output port Assertion
assert ((reset_i === ‘X) || (reset_i === 1’b1) || (w_addr_i < els_p)); assert ((reset_i === ‘X) || (reset_i === 1’b1) || (~(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p && !disable_collision_warning_p)));
Details & Circuit structure
bsg_mem_1r1w_sync_mask_write_bit_synth¶
Overview
This module is 1 read-port and 1 write-port ram with mask, and reads are synchronous. This is synth version.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 read_write_same_addr_p input data width 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) harden_p use harden IP or not 0 disable_collision_warning_p detection signal 1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_mask_i width_p data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r_v_i 1 data input port r_addr_i addr_width_lp data input port OUTPUT r_data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_1r1w_sync_mask_write_var¶
Overview
This module is 1 read-port and 1 write-port ram, and reads are synchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 els_p input data width -1 chunk_size_lp cycle range width_p / mask_width_p addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) harden_p use harden IP or not 0 read_write_same_addr_p detection signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_mask_i width_p data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r_v_i 1 data input port r_addr_i addr_width_lp data input port OUTPUT r_data_o width_p data output port Assertion
assert ((reset_i === ‘X) || (reset_i === 1’b1) || (w_addr_i < els_p)); assert ((reset_i === ‘X) || (reset_i === 1’b1) || ~(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p && !disable_collision_warning_p));
Details & Circuit structure
bsg_mem_1rw_sync_synth¶
Overview
This module is synchronous 1-port ram, and only one read or one write may be done per cycle.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 latch_last_read_p select signal 0 addr_width_lp cycle range `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT v_i 1 data input port data_i width_p data input port addr_i addr_width_lp data input port w_i 1 data input port OUTPUT data_o width_p data output port Assertion
assert ( (v_i !== 1’b1) || (reset_i === ‘X) || (reset_i === 1’b1) || (addr_i < els_p));
Details & Circuit structure
bsg_mem_1rw_sync¶
Overview
This module is synchronous 1-port ram, and only one read or one write may be done per cycle.
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port addr_i addr_width_lp data input port v_i 1 data input port w_i 1 data input port OUTPUT data_o width_p data output port
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 latch_last_read_p select signal 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) enable_clock_gating_p select signal 0
Assertion
assert ( (v_i !== 1’b1) || (reset_i === ‘X) || (reset_i === 1’b1) || (addr_i < els_p));
Details & Circuit structure
bsg_mem_1rw_sync_banked¶
Overview
This module can be used for breaking a big SRAM block intosmaller blocks.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” els_p input data width “inv” latch_last_read_p select signal 0 num_width_bank_p cycle range 1 num_depth_bank_p internal signal bit width 1 addr_width_lp input and output data width `BSG_SAFE_CLOG2(els_p) bank_depth_lp input data width els_p/num_depth_bank_p bank_addr_width_lp internal signal bit width `BSG_SAFE_CLOG2(bank_depth_lp) depth_bank_idx_width_lp internal signal bit width `BSG_SAFE_CLOG2(num_depth_bank_p) bank_width_lp select signal width_p/num_width_bank_p
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port addr_i addr_width_lp data input port v_i 1 data input port w_i 1 data input port OUTPUT data_o width_p data output port Assertion
assert(els_p % num_depth_bank_p == 0); assert(width_p % num_width_bank_p == 0);
Details & Circuit structure
bsg_mem_1rw_sync_mask_write_bit¶
Overview
This module is a synchronous 1-port ram with mask, and only one read or one write may be done per cycle.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 latch_last_read_p select signal 0 enable_clock_gating_p select signal 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port addr_i addr_width_lp data input port v_i 1 data input port w_mask_i width_p data input port w_i 1 data input port OUTPUT data_o width_p data output port Assertion
assert ((reset_i === ‘X) || (reset_i === 1’b1) || (addr_i < els_p));
Details & Circuit structure
bsg_mem_1rw_sync_mask_write_bit_banked¶
Overview
This module can be used for breaking a big SRAM block into smaller blocks.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” els_p input data width “inv” latch_last_read_p select signal 0 num_width_bank_p cycle range 1 num_depth_bank_p internal signal bit width 1 addr_width_lp input and output data width `BSG_SAFE_CLOG2(els_p) bank_depth_lp input data width els_p/num_depth_bank_p bank_addr_width_lp internal signal bit width `BSG_SAFE_CLOG2(bank_depth_lp) depth_bank_idx_width_lp internal signal bit width `BSG_SAFE_CLOG2(num_depth_bank_p) bank_width_lp select signal width_p/num_width_bank_p
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port addr_i addr_width_lp data input port v_i 1 data input port w_mask_i width_p data input port w_i 1 data input port OUTPUT data_o width_p data output port Assertion
assert(els_p % num_depth_bank_p == 0); assert(width_p % num_width_bank_p == 0);
Details & Circuit structure
bsg_mem_1rw_sync_mask_write_bit_synth¶
Overview
This module is synchronous 1-port ram, and only one read or one write may be done per cycle.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p internal signal bit width -1 latch_last_read_p select signal 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port addr_i addr_width_lp data input port v_i 1 data input port w_mask_i width_p data input port w_i 1 data input port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_1rw_sync_mask_write_byte¶
Overview
This module is synchronous 1-port ram with mask, and only one read or one write may be done per cycle. For each bit sey in the mask, a byte is written.
Parameter
NAME DESCRIPTION DEFAULT els_p input data width -1 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) data_width_p input and output data width -1 latch_last_read_p select signal 0 write_mask_width_lp input data width data_width_p>>3 enable_clock_gating_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i data_width_p data input port addr_i addr_width_lp data input port v_i 1 data input port w_mask_i write_mask_width_lp data input port w_i 1 data input port OUTPUT data_o data_width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_1rw_sync_mask_write_byte_banked¶
Overview
This module is synchronous 1-port ram with mask, and only one read or one write may be done per cycle. For each bit sey in the mask, a byte is written.
Parameter
NAME DESCRIPTION DEFAULT data_width_p input and output data width “inv” els_p input data width “inv” latch_last_read_p input data width 0 write_mask_width_lp input data width data_width_p>>3 num_width_bank_p cycle range 1 num_depth_bank_p internal signal bit width 1 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) bank_depth_lp input data width els_p/num_depth_bank_p bank_addr_width_lp internal signal bit width `BSG_SAFE_CLOG2(bank_depth_lp) depth_bank_idx_width_lp internal signal bit width `BSG_SAFE_CLOG2(num_depth_bank_p) bank_width_lp select signal data_width_p/num_width_bank_p bank_mask_width_lp signal bit wide range bank_width_lp>>3
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i data_width_p data input port addr_i addr_width_lp data input port v_i 1 data input port w_mask_i write_mask_width_lp data input port w_i 1 data input port OUTPUT data_o data_width_p data output port Assertion
assert (data_width_p % 8 == 0); assert(els_p % num_depth_bank_p == 0); assert(data_width_p % num_width_bank_p == 0);
Details & Circuit structure
bsg_mem_1rw_sync_mask_write_byte_synth¶
Overview
This module is synchronous 1-port ram with mask for synthesizable internal version, and only one read or one write may be done per cycle. For each bit sey in the mask, a byte is written.
Parameter
NAME DESCRIPTION DEFAULT els_p input data width -1 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) latch_last_read_p select signal 0 data_width_p input data width -1 write_mask_width_lp input data width data_width_p>>3
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i data_width_p data input port addr_i addr_width_lp data input port v_i 1 data input port write_mask_i write_mask_width_lp data input port w_i 1 data input port OUTPUT data_o data_width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_1rw_sync_mask_write_var¶
Overview
This module is a synchronous 1-port ram with mask, and only one read or one write may be done per cycle.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 mask_width_p input data width -1 els_p select signal -1 chunk_size_lp cycle range width_p / mask_width_p addr_width_lp input data width `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port addr_i addr_width_lp data input port v_i 1 data input port w_mask_i width_p data input port w_i 1 data input port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_2r1w_sync¶
Overview
This module is a 2 read-port and 1 write-port ram, and reads are synchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 read_write_same_addr_p None 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) harden_p use harden IP or not 0 enable_clock_gating_p select signal `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r0_v_i 1 data input port r0_addr_i addr_width_lp data input port r1_v_i 1 data input port r1_addr_i addr_width_lp data input port OUTPUT r0_data_o width_p data output port r1_data_o width_p data output port Assertion
assert (w_addr_i < els_p) assert (~(r0_addr_i == w_addr_i && w_v_i && r0_v_i && !read_write_same_addr_p)) assert (~(r1_addr_i == w_addr_i && w_v_i && r1_v_i && !read_write_same_addr_p))
Details & Circuit structure
bsg_mem_2r1w_sync_synth¶
Overview
This module is a 2 read-port and 1 write-port ram, and reads are synchronous.This is synthesize version.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 read_write_same_addr_p None 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) harden_p use harden IP or not 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r0_v_i 1 data input port r0_addr_i addr_width_lp data input port r1_v_i 1 data input port r1_addr_i addr_width_lp data input port OUTPUT r0_data_o width_p data output port r1_data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_3r1w_sync¶
Overview
This module is a 3 read-port, 1 write-port ram, and reads are synchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p mem dimensions -1 read_write_same_addr_p None 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) harden_p use harden IP or not 0 enable_clock_gating_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r0_v_i 1 data input port r0_addr_i addr_width_lp data input port r1_v_i 1 data input port r1_addr_i addr_width_lp data input port r2_v_i 1 data input port r2_addr_i addr_width_lp data input port OUTPUT r0_data_o width_p data output port r1_data_o width_p data output port r2_data_o width_p data output port Assertion
assert (w_addr_i < els_p); assert (~(r0_addr_i == w_addr_i && r0_v_i && !read_write_same_addr_p)); assert (~(r1_addr_i == w_addr_i && r1_v_i && !read_write_same_addr_p)); assert (~(r2_addr_i == w_addr_i && r2_v_i && !read_write_same_addr_p));
Details & Circuit structure
bsg_mem_3r1w_sync_synth¶
Overview
This module is a 3 read-port, 1 write-port ram, and reads are synchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p mem dimensions -1 read_write_same_addr_p None 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) harden_p use harden IP or not 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r0_v_i 1 data input port r0_addr_i addr_width_lp data input port r1_v_i 1 data input port r1_addr_i addr_width_lp data input port r2_v_i 1 data input port r2_addr_i addr_width_lp data input port OUTPUT r0_data_o width_p data output port r1_data_o width_p data output port r2_data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_banked_crossbar¶
Overview
This module is a bank mem banked crossbar.
Parameter
NAME DESCRIPTION DEFAULT i_els_p input and output data width -1 o_els_p input and output data width -1 rr_lo_hi_p select signal “inv” lg_o_els_lp input data width `BSG_SAFE_CLOG2(o_els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port reverse_pr_i 1 data input port valid_i i_els_p data input port sel_io_i i_els_p*lg_o_els_lp data input port ready_i o_els_p data input port OUTPUT yumi_o i_els_p data output port valid_o o_els_p data output port grants_oi_one_hot_o o_els_p*i_els_p data output port Assertion
None
Details & Circuit structure
bsg_nonsynth_mem_1r1w_sync_dma¶
Overview
This module is synchronous 1 read-port and 1 write-port mem.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” els_p input data width -1 id_p input and output data width “inv” data_width_in_bytes_lp cycle range width_p>>3 write_mask_width_lp input data width data_width_in_bytes_lp addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) byte_offset_width_lp internal signal bit wide range `BSG_SAFE_CLOG2(data_width_in_bytes_lp) init_mem_p chandle parameter 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT r_v_i 1 data input port r_addr_i addr_width_lp data input port w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma¶
Overview
This module is synchronous 1 read-port and 1 write-port mem with mask.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” els_p input data width -1 id_p input and output data width “inv” data_width_in_bytes_lp cycle range width_p>>3 write_mask_width_lp input data width data_width_in_bytes_lp addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) byte_offset_width_lp internal signal bit wide range `BSG_SAFE_CLOG2(data_width_in_bytes_lp) init_mem_p chandle parameter 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT r_v_i 1 data input port r_addr_i addr_width_lp data input port w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port w_mask_i write_mask_width_lp data input port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_nonsynth_mem_1rw_sync_assoc¶
Overview
This module is for simulating arbitrarily large memories.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” addr_width_p input data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port addr_i addr_width_p data input port v_i 1 data input port w_i 1 data input port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_nonsynth_mem_1rw_sync_mask_write_byte_assoc¶
Overview
This module is for simulating arbitrarily large memories with mask.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” addr_width_p input data width “inv” write_mask_width_lp input data width data_width_p>>3
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port addr_i addr_width_p data input port v_i 1 data input port w_i 1 data input port write_mask_i write_mask_width_lp data input port OUTPUT data_o data_width_p data output port Assertion
None
Details & Circuit structure
bsg_nonsynth_mem_1rw_sync_mask_write_byte_dma¶
Overview
This module implements synchronous byte mem with mask.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” els_p input data width -1 id_p input and output data width “inv” data_width_in_bytes_lp cycle range width_p>>3 write_mask_width_lp input data width data_width_in_bytes_lp addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) byte_offset_width_lp internal signal bit wide range `BSG_SAFE_CLOG2(data_width_in_bytes_lp) init_mem_p chandle parameter 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port addr_i addr_width_lp data input port v_i 1 data input port w_i 1 data input port w_mask_i write_mask_width_lp data input port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_misc¶
Multiplier Releted Unint¶
bsg_mul_comp42¶
Overview
This module is a adder for mul.
Parameter
None
Port
TYPE NAME WIDTH DESCRIPTION INPUT i 4 data input port cr_i 1 data input port OUTPUT cl_o 1 data output port c_o 1 data output port s_o 1 data output port Assertion
None
Details & Circuit structure
bsg_mul_comp42_rep¶
Overview
This module combine vectors of results from blocks.
Parameter
NAME DESCRIPTION DEFAULT blocks_p signal width 1 harden_p use harden IP or not 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT i 4*blocks_p data input port cr_i 1 data input port OUTPUT cl_o 1 data output port c_o blocks_p data output port s_o blocks_p data output port Assertion
None
Details & Circuit structure
bsg_mul_booth_4_block¶
Overview
This module is a block of mul_booth_4.
Parameter
NAME DESCRIPTION DEFAULT S_above_vec_p select signal 4’b0000 dot_bar_vec_p select signal 4’b0000 B_vec_p select signal 4’b0000 one_vec_p select signal 4’b0000
Port
TYPE NAME WIDTH DESCRIPTION INPUT SDN_i 15 data input port cr_i 1 data input port y_i 8 data input port OUTPUT cl_o 1 data output port c_o 1 data output port s_o 1 data output port Assertion
None
Details & Circuit structure
bsg_mul_booth_4_block_rep¶
Overview
This module combine vectors of results from blocks.
Parameter
NAME DESCRIPTION DEFAULT blocks_p input and output data width 1 S_above_vec_p select signal 0 dot_bar_vec_p select signal 0 B_vec_p select signal 0 one_vec_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT SDN_i 15 data input port cr_i 1 data input port y_vec_i 8*blocks_p data input port OUTPUT cl_o 1 data output port c_o blocks_p data output port s_o blocks_p data output port Assertion
None
Details & Circuit structure
bsg_imul_iterative¶
Overview
This is an 32bit integer iterative multiplier, capable of signed & unsigned multiplication.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width 32
Port
Assertion
None
Details & Circuit structure
bsg_mul_array¶
Overview
This module is a pipelined unsigned array multiplier.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” pipeline_p selcet signal 1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET rst_i 1 reset input port INPUT v_i 1 data input port a_i width_p data input port b_i width_p data input port OUTPUT o 2*width_p data output port Assertion
None
Details & Circuit structure
bsg_mul_array_row¶
Overview
This module is a pipelined adder.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” row_idx_p input and output data width “inv” pipeline_p selcet signal “inv”
Port
Assertion
None
Details & Circuit structure
bsg_mul_pipelined¶
Overview
This is a library of multipliers.
bsg_mul_synth¶
Overview
This is synthesized multiplier.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port b_i width_p data input port OUTPUT o 2*width_p data output port Assertion
None
Details & Circuit structure
bsg_mul¶
Overview
This module is a pipeline multiplier.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT x_i width_p data input port y_i width_p data input port signed_i 1 data input port OUTPUT z_o width_p data output port Assertion
None
Details & Circuit structure
Logic Gate Releted Unit¶
bsg_abs¶
Overview
This module calculates the absolute value of signed integers.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port OUTPUT a_o width_p data output port Assertion
None
Details & Circuit structure
bsg_and¶
Overview
This is a two-input AND gate.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port b_i width_p data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_inv¶
Overview
This is an inverter.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_nand¶
Overview
This is a two-input NAND gate.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port b_i width_p data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_nor2¶
Overview
This is a two-input NOR gate.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port b_i width_p data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_nor3¶
Overview
This is a three-input NOR gate.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port b_i width_p data input port c_i width_p data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_xnor¶
Overview
This is a two-input XNOR gate.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port b_i width_p data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_xor¶
Overview
This is a two-input XOR gate.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port b_i width_p data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
Adder Releted Unit¶
bsg_adder_cin¶
Overview
This module implements a simple adder with cin.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port b_i width_p data input port cin_i 1 data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_adder_one_hot¶
Overview
This module calculates the absolute value of signed integers.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port b_i width_p data input port OUTPUT o output_width_p data output port Assertion
assert (output_width_p >= width_p)
Details & Circuit structure
bsg_adder_ripple_carry¶
Overview
This is a traveling wave carry adder.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port b_i width_p data input port OUTPUT s_o width_p data output port c_o 1 data output port Assertion
None
Details & Circuit structure
Encoder Releted Unit¶
bsg_priority_encode¶
Overview
The function of this module is to encode and output the input data twice.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” lo_to_hi_p control signal “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT v_o 1 data output port addr_o `BSG_SAFE_CLOG2(width_p)-1 data output port Assertion
None
Details & Circuit structure
bsg_priority_encode_one_hot_out¶
Overview
This module encodes by one-hot and outputs the input data.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” lo_to_hi_p control signal “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT v_o 1 data output port o width_p data output port Assertion
None
Details & Circuit structure
bsg_arb_fixed¶
Overview
This is a priority encoder that can control the output to all 0 or the encoded result.
Parameter
NAME DESCRIPTION DEFAULT inputs_p input and output data width “inv” lo_to_hi_p control signal “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT ready_i 1 data input port reqs_i width_p data input port OUTPUT grants_0 width_p data output port Assertion
None
Details & Circuit structure
bsg_arb_round_robin¶
Overview
This is a circular encoder.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock port RESET reset_i 1 reset port INPUT reqs_i width_p data input port yumi_i 1 data input port OUTPUT grants_o width_p data output port Assertion
None
Details & Circuit structure
bsg_arrary_concentrate¶
Overview
This module outputs an input array of a certain number of digits.
Parameter
NAME DESCRIPTION DEFAULT pattern_els_p input and output data width “inv” width_p input and output data width “inv” dense_els_lp input data width $bits(pattern_els_p) sparse_els_lp output data width `BSG_COUNTONES_SYNTH(pattern_els_p)
Port
TYPE NAME WIDTH DESCRIPTION INPUT i dense_els_lp*width_p data input port OUTPUT o sparse_els_lp*width_p data output port Assertion
None
Details & Circuit structure
bsg_array_reverse¶
Overview
This module reverse the input array for output.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” els_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT i els_p*width_p data input port OUTPUT o els_p*width_p data output port Assertion
None
Details & Circuit structure
bsg_binary_plus_one_to_gray¶
Overview
This module converts binary input + 1 to gray code.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. -1
Port
TYPE NAME WIDTH DESCRIPTION INPUT binary_i width_p data input port OUTPUT gray_o width_p data output port Assertion
None
Details & Circuit structure
Buffer Releted Unit¶
bsg_buf¶
Overview
This is a buffer circuit.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_buf_ctrl¶
Overview
This module buff 1 bit control signal to width_p vector.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT i 1 data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_clkbuf¶
Overview
This module is a buffer.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. 1 harden_p use harden IP or not 1 strength_p no 8
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg¶
bsg_concentrate_static¶
Overview
This module given a bunch of signals, and a bitvector parameter,concentrate those bits together into a more condensed vector.
Parameter
NAME DESCRIPTION DEFAULT pattern_els_p input and output data width “inv” width_lp input data width $bits(pattern_els_p) set_els_lp output data width `BSG_COUNTONES_SYNTH(pattern_els_p)
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_lp data input port OUTPUT o set_els_lp data output port Assertion
None
Details & Circuit structure
bsg¶
bsg_circular_ptr¶
Overview
This module implements a circular pointer that can be incremented by at most max_add_p and points to slots_p slots.
Parameter
Name DESCRIPTION DEFAULT slots_p output data width -1 max_add_p input data width -1 ptr_width_lp output data width -1
Port
Type NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT add_i $clog2(max_add_p+1) data input port OUTPUT o ptr_width_lp data output port n_o ptr_width_lp data output port Assertion
None
Details & Circuit structure
bsg_clkgate_optional¶
Overview
This is an integrated clock cell using a negative latch and an AND gate.
Parameter
None
Port
Type NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port INPUT en_i 1 data input port bypass_i 1 data input port OUTPUT gated_clock_o 1 data output port Assertion
None
Details & Circuit structure
Counter Releted Unit¶
bsg_counter_clear_up¶
Overview
This counter counts up and is occasionally cleared.
Parameter
NAME DESCRIPTION DEFAULT max_val_p set the max value -1 init_val_p set the initial value of the count `BSG_UNDEFINED_IN_SIM(‘0) ptr_width_lp output data width `BSG_SAFE_CLOG2(max_val_p+1) disable_overflow_warning_p overflow signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port CLEAR clear_i 1 clear input port INPUT up_i 1 data input port OUTPUT count_o ptr_width_lp data output port Assertion
None
Details & Circuit structure
bsg_counter_clear_up_one_hot¶
Overview
This counter is a one hot counter only one output bit is set at any time.
Parameter
NAME DESCRIPTION DEFAULT max_val_p set the max value -1 init_val_p set the initial value of the count (width_lp) ‘ (1) width_lp output data width max_val_p+1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port CLEAR clear_i 1 clear input port INPUT up_i 1 data input port OUTPUT count_o width_lp data output port Assertion
None
Details & Circuit structure
bsg_counter_clock_downsample¶
Overview
This counter will counter down from val_i to 0.When the counter hits 0, the output clk_r_o will invert.
Parameter
NAME DESCRIPTION DEFAULT width_p input data width “inv” harden_p use harden IP or not 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT val_i width_p data input port OUTPUT clk_r_o 1 data output port Assertion
None
Details & Circuit structure
bsg_counter_dynamic_limit¶
Overview
This module is a counter with dynamic limit that repeats counting from zero to overflow value.
Parameter
NAME DESCRIPTION DEFAULT width_p input data width -1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT limit_i width_p data input port OUTPUT counter_o width_p data output port Assertion
None
Details & Circuit structure
bsg_counter_dynamic_limit_en¶
Overview
This module implements simple counter with enable signal and dynamic overflow limit.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT en_i 1 setting port limit_i width_p data input port OUTPUT counter_o width_p data output port overflowed_o 1 data output port Assertion
None
Details & Circuit structure
bsg_counter_overflow_en¶
Overview
This is a counter with an overflow flag bit.
Parameter
NAME DESCRIPTION DEFAULT max_val_p max value -1 init_val_p initial value -1 ptr_width_lp output data width `BSG_SAFE_CLOG2(max_val_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT en_i 1 setting port OUTPUT count_o ptr_width_lp data output port overflow_o 1 data output port Assertion
None
Details & Circuit structure
bsg_counter_overflow_set_en¶
Overview
This is a counter with a set signal and an overflow flag signal.
Parameter
NAME DESCRIPTION DEFAULT max_val_p max value -1 lg_max_val_lp input and output data width `BSG_SAFE_CLOG2(max_val_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT set_i 1 setting port val_i lg_max_val_lp data input port OUTPUT count_o lg_max_val_lp data output port overflow_o 1 data output port Assertion
None
Details & Circuit structure
bsg_counter_set_down¶
Overview
This is a decrement counter with a set.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” init_val_p initial value ‘0 set_and_down_exclusive_p flag bit 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT set_i 1 setting port val_i width_p data input port down_i 1 data input port count_o width_p data output port Assertion
None
Details & Circuit structure
bsg_counter_set_en¶
Overview
This is a decrement counter with a set.
Parameter
NAME DESCRIPTION DEFAULT max_val_p input and output data width “inv” lg_max_val_lp input and output data width `BSG_SAFE_CLOG2(max_val_p) reset_val_p reset value 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT set_i 1 setting port val_i lg_max_val_lp data input port en_i 1 data input port count_o lg_max_val_lp data output port Assertion
None
Details & Circuit structure
bsg_counter_up_down¶
Overview
This is an up-down counter with initial and max values.
Parameter
NAME DESCRIPTION DEFAULT max_val_p max value -1 init_val_p initial value -1 max_step_p input data width -1 step_width_lp input data width `BSG_WIDTH(max_step_p) ptr_width_lp output data width `BSG_WIDTH(max_val_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT up_i step_width_lp data input port down_i step_width_lp data input port OUTPUT count_o ptr_width_lp data output port Assertion
None
Details & Circuit structure
bsg_counter_up_down_variable¶
Overview
This is an up-down counter with initial and max values.
Parameter
NAME DESCRIPTION DEFAULT max_val_p max value -1 init_val_p initial value -1 max_step_p input data width -1 step_width_lp input data width `BSG_WIDTH(max_step_p) ptr_width_lp output data width `BSG_WIDTH(max_val_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT up_i step_width_lp data input port down_i step_width_lp data input port OUTPUT count_o ptr_width_lp data output port Assertion
None
Details & Circuit structure
bsg_counting_leading_zeros¶
Overview
This is a priority encoder that encodes the input reversed first.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port OUTPUT num_zero_o `BSG_SAFE_CLOG2(width_p) data output port Assertion
None
Details & Circuit structure
bsg_cycle_counter¶
Overview
This is a loop counter.
Parameter
NAME DESCRIPTION DEFAULT i_els_p input and output data width -1 o_els_p input and output data width -1 width_p input and output data width -1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port OUTPUT ctr_r_o width_p data output port Assertion
None
Details & Circuit structure
Crossbar Releted Unit¶
bsg_crossbar_control_basic_o_by_i¶
Overview
This module generates the control signals for bsg_router_crossbar_o_by_i.
Parameter
NAME DESCRIPTION DEFAULT i_els_p input and output data width “inv” o_els_p input and output data width “inv” lg_o_els_lp input data width `BSG_SAFE_CLOG2(o_els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT valid_i i_els_p data input port sel_io_i i_els_p*lg_o_els_lp data input port ready_and_i o_els_p data input port OUTPUT yumi_o i_els_p data output port valid_o step_width_lp data output port grants_oi_one_hot_o o_els_p*i_els_p data output port Assertion
None
Details & Circuit structure
bsg_crossbar_o_by_i¶
Overview
This is a benes network implementation.
Parameter
NAME DESCRIPTION DEFAULT i_els_p input and output data width -1 o_els_p input and output data width -1 width_p input and output data width -1
Port
TYPE NAME WIDTH DESCRIPTION INPUT i i_els_p*width_p data input port sel_oi_one_hot_i o_els_p*i_els_p data input port OUTPUT o o_els_p*width_p data output port Assertion
None
Details & Circuit structure
DFF & Latch¶
bsg_dff¶
Overview
This is a DFF without other ports. It is triggered by the positive edge of input clock.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port -1 harden_p use harden IP or not 0 strength_p drive strength 1 Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 input clock INPUT data_i width_p input data OUTPUT data_o width_p output data Assertion
None
Details & Circuit structure
bsg_dff_en¶
Overview
This is a DFF with an enable port. It is triggered by the positive edge of input clock.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port “inv” harden_p use harden IP or not 1 strength_p drive strength 1 Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 input clock INPUT data_i width_p input data en_i 1 enable OUTPUT data_o width_p output data Assertion
None
Details & Circuit structure
bsg_dff_reset¶
Overview
This is a DFF with a reset port. It is triggered by the positive edge of input clock. The reset is synchronous and active high.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port -1 harden_p use harden IP or not 0 reset_val_p initial value of data_o if reset 0 Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 input clock RESET reset_i 1 reset INPUT data_i width_p input data OUTPUT data_o width_p output data Assertion
None
Details & Circuit structure
bsg_dff_reset_en¶
Overview
This is a DFF with reset and enable ports. It is triggered by the positive edge of input clock. The reset is synchronous and active high.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port “inv” harden_p use harden IP or not 0 reset_val_p initial value of output data when reset 0 Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 input clock RESET reset_i 1 reset INPUT data_i width_p input data en_i 1 enable OUTPUT data_o width_p output data Assertion
None
Details & Circuit structure
bsg_dff_negedge_reset¶
Overview
This is a DFF with a reset port. It is triggered by the negative edge of input clock. The reset is synchronous and active high.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port -1 harden_p use harden IP or not 0 Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 input clock RESET reset_i 1 reset INPUT data_i width_p input data OUTPUT data_o width_p output data Assertion
None
Details & Circuit structure
bsg_dff_gatestack¶
Overview
This is a set of DFFs. Each DFF is triggered by the positive edge of the its corresponding bit of i1. There is no reset or enable signals for these DFFs.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port “inv” harden_p use harden IP or not 1 Port
TYPE NAME WIDTH DESCRIPTION INPUT i0 width_p input data i1 width_p data transmission trigger, clocks for each bit of input OUTPUT o width_p output data Assertion
None
Details & Circuit structure
bsg_dff_chain¶
Overview
This is a DFF chain. Input data will be stored num_stages_p times in the DFF chain. All DFFs are triggered by the positive edge of input clock. There are no reset and enable signals in each DFF.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port -1 num_stages_p stage number of DFFs 1 Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 input clock INPUT data_i width_p input data OUTPUT data_o width_p output data Assertion
None
Details & Circuit structure
Input data will be transmitted stage by stage without any stall. If num_stages_p is 0, input data is assigned to output port directly without any registers.
bsg_dff_en_bypass¶
Overview
This is a DFF with a bypass lane. The DFF is triggered by positive edge of the clock. If the DFF is enabled, the output data is changed to be the input data immediately.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port “inv” harden_p use harden IP or not 1 strength_p drive strength 1 Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 input clock INPUT data_i width_p input data en_i 1 enable OUTPUT data_o width_p output data Assertion
None
Details & Circuit structure
When enable is 1, input data is stored into the register and bypassed to the output port at the same time. The module consists of a bsg_dff_en and a bypass lane.
bsg_dff_reset_en_bypass¶
Overview
This is a DFF with a bypass lane and a reset port. The DFF is triggered by positive edge of the clock. If the DFF is enabled, the output data is changed to be the input data immediately. The reset is synchronous and active high.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port “inv” harden_p use harden IP or not 0 reset_val_p initial value of output data when reset 0 Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 input clock RESET reset_i 1 reset INPUT data_i width_p input data en_i 1 enable OUTPUT data_o width_p output data Assertion
None
Details & Circuit structure
When enable is 1, input data is stored into the register and bypassed to the output port at the same time. The module consists of a bsg_dff_reset_en and a bypass lane.
bsg_dff_reset_set_clear¶
Overview
This is a DFF with reset, set and clear ports. It is triggered by positive edge of the clock. The reset is synchronous and active high.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port “inv” clear_over_set_p priorities of clear. If it is 1, clear is prio to set 0 Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 input clock RESET reset_i 1 reset INPUT data_i width_p input data set_i width_p set enable clear_i width_p clear enable OUTPUT data_o width_p output data Assertion
None
Details & Circuit structure
Reset value of the DFF is ‘0. Each bit of the input data has a corresponding set and clear signal. If set_i[i] and clear_i[i] are both 1’b1: a) data_o[i] is 0, when clear_over_set_p is 1. b)data_o[i] is 1, when clear_over_set_p is 0.
bsg_dlatch¶
Overview
This is a dlatch. The clock is active high.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port “inv” i_know_this_is_a_bad_idea_p show the necessary to instantiate a latch 0 Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 input clock INPUT data_i width_p input data OUTPUT data_o width_p output data Assertion
i_know_this_is_a_bad_idea_p == 0
The default value of i_know_this_is_a_bad_idea_p is 0. If users want to instantiate a latch, it is necessary override i_know_this_is_a_bad_idea_p to show that the instantiation is inevitable and the user know all adverse effects.
Details & Circuit structure
Decode Releted Unit¶
bsg_decode¶
Overview
This unit is a decoder.
Parameter
NAME DESCRIPTION DEFAULT num_out_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT i `BSG_SAFE_CLOG2(num_out_p) data input port OUTPUT o num_out_p data output port Assertion
None
Details & Circuit structure
bsg_decode_with_v¶
Overview
This unit is a decoder and can control whether the output is zero or decoder.
Parameter
NAME DESCRIPTION DEFAULT num_out_p input and output data width -1
Port
TYPE NAME WIDTH DESCRIPTION INPUT i `BSG_SAFE_CLOG2(num_out_p) data input port v_i 1 control port OUTPUT o num_out_p data output port Assertion
None
Details & Circuit structure
bsg_encode_one_hot¶
Overview
This is a one hot encoder.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width 8 o_to_hi_p select signal 1 debug_p debug signal 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT addr_o `BSG_SAFE_CLOG2(width_p) data output port v_o 1 data output port Assertion
None
Details & Circuit structure
bsg_expand_bitmask¶
Overview
This module expands each bit in the input vector by the factor of expand_p.
Parameter
NAME DESCRIPTION DEFAULT in_width_p input and output data width “inv” expand_p select signal “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT i in_width_p data input port OUTPUT o in_width_p*expand_p data output port Assertion
None
Details & Circuit structure
bsg_gray_to_binary¶
Overview
This module converts gray code into binary code.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1
Port
TYPE NAME WIDTH DESCRIPTION INPUT gray_i width_p data input port OUTPUT binary_o width_p data output port Assertion
None
Details & Circuit structure
Edge¶
bsg_edge_detect¶
Overview
This unit produces the fall edge.
Parameter
NAME DESCRIPTION DEFAULT falling_not_rising_p input and output data width 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT sig_i 1 data input port OUTPUT detect_o 1 data output port Assertion
None
Details & Circuit structure
Hash Bank Releted Unit¶
bsg_hash_bank¶
Overview
This module takes a binary address, and a constant number of banks, and then hashes the address across the banks efficiently; outputing the bank #, and the index at that bank.
Parameter
NAME DESCRIPTION DEFAULT banks_p input and output data width “inv” width_p input and output data width “inv” index_width_lp output data width $clog2((2**width_p+banks_p-1)/banks_p) lg_banks_lp output data width `BSG_SAFE_CLOG2(banks_p) debug_lp debug signal 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT bank_o lg_banks_lp data output port index_o index_width_lp data output port Assertion
None
Details & Circuit structure
bsg_hash_bank_reverse¶
Overview
This module is the inverse,taking a bank number and an index, and producing the original address.
Parameter
NAME DESCRIPTION DEFAULT banks_p input and output data width “inv” width_p input and output data width “inv” index_width_lp input data width $clog2((2**width_p+banks_p-1)/banks_p) lg_banks_lp input data width `BSG_SAFE_CLOG2(banks_p) debug_lp debug signal 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT index_i index_width_lp data input port bank_i lg_banks_lp data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
Divider Releted Unit¶
bsg_idiv_iterative¶
Overview
This module is an N-bit integer iterative divider, capable of signed & unsigned division.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width 32
Port
Assertion
None
Details & Circuit structure
bsg_idiv_iterative_controller¶
Overview
The controller of bsg_idiv_iterative module.
Parameter
NAME DESCRIPTION DEFAULT width_p Internal signal width 32
Port
Assertion
None
Details & Circuit structure
Comparator Releted Unit¶
bsg_less_than¶
Overview
This is a two input comparer.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port OUTPUT b_i width_p data output port Assertion
None
Details & Circuit structure
Linear Shifter Releted Uint¶
bsg_level_shift_up_down_sink¶
Overview
This module represents a simple level shifter.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT v0_data_i width_p data input port v1_en_i 1 data input port OUTPUT v1_data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_level_shift_up_down_source¶
Overview
This module represents a simple level shifter.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT v0_data_i width_p data input port v1_en_i 1 data input port OUTPUT v1_data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_lfsr¶
Overview
This module is a LFSR.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 init_val_p initial signal 1 xor_mask_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk 1 clock input port RESET reset_i 1 reset input port INPUT yumi_i 1 data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
Arbitration Releted Unit¶
bsg_locking_arb_fixed¶
Overview
This module is a fixed priority arbitration unit.
Parameter
NAME DESCRIPTION DEFAULT inputs_p input and output data width “inv” lo_to_hi_p select signal 1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk 1 clock input port INPUT ready_i 1 data input port unlock_i 1 data input port reqs_i inputs_p data input port OUTPUT grants_o inputs_p data output port Assertion
None
Details & Circuit structure
Pseudo_Tree Releted Unit¶
bsg_lru_pseudo_tree_backup¶
Overview
This module is a tree pseudo LRU backup finder.
Parameter
NAME DESCRIPTION DEFAULT ways_p input and output data width “inv” lg_ways_lp cyclic variable `BSG_SAFE_CLOG2(ways_p)
Port
TYPE NAME WIDTH DESCRIPTION INPUT disabled_ways_i ways_p data input port OUTPUT modify_mask_o ways_p data output port modify_data_o ways_p data output port Assertion
None
Details & Circuit structure
bsg_lru_pseudo_tree_decode¶
Overview
This module is a Pseudo-Tree-LRU decode unit.
Parameter
NAME DESCRIPTION DEFAULT ways_p output data width “inv” lg_ways_lp input data width `BSG_SAFE_CLOG2(ways_p)
Port
TYPE NAME WIDTH DESCRIPTION INPUT way_id_i lg_ways_lp data input port OUTPUT data_o ways_p data output port mask_o ways_p data output port Assertion
None
Details & Circuit structure
bsg_lru_pseudo_tree_encode¶
Overview
This module is a Pseudo-Tree-LRU encode unit.
Parameter
NAME DESCRIPTION DEFAULT ways_p input data width “inv” lg_ways_lp output data width `BSG_SAFE_CLOG2(ways_p)
Port
TYPE NAME WIDTH DESCRIPTION INPUT lru_i ways_p data input port OUTPUT way_id_o lg_ways_lp data output port Assertion
None
Details & Circuit structure
Selector Releted Unit¶
bsg_mux¶
Overview
This is a selector.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” els_p input data width “inv” harden_p use harden IP or not 0 balanced_p assert signal 0 lg_els_lp input data width `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION INPUT data_i els_p*width_p data input port sel_i lg_els_lp data input port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mux2_gatestack¶
Overview
This is a two-selection selector with width of width_p bits.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT i0 width_p data input port i1 width_p data input port i2 width_p select port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_muxi2_gatestack¶
Overview
This is a two-selection selector with width of width_p bits.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT i0 width_p data input port i1 width_p data input port i2 width_p select port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_mux_bitwise¶
Overview
This module is a two-to-one data selector with width_p bit width.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT data0_i width_p data input port data1_i width_p data input port sel_i width_p sel input port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mux_butterfly¶
Overview
This module has stages of mux which interleaves input data.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” els_p input and output data width. “inv” lg_els_lp input data width. `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION INPUT data1_i els_p*width_p data input port sel_i lg_els_lp sel input port OUTPUT data_o els_p*width_p data output port Assertion
None
Details & Circuit structure
bsg_mux_one_hot¶
Overview
This module is a multi-bit selector with one-hot encoding.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” els_p input and output data width. 1 harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT data_i els_p*width_p data input port sel_one_hot_i els_p sel input port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mux_segmented¶
Overview
This is a two-selection selector with width of segment_width_p bits.
Parameter
NAME DESCRIPTION DEFAULT data_width_lp input and output data width. segments_p*segment_width_p segments_p number of segments “inv” segment_width_p width of each segment “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT data0_i data_width_lp data input port data1_i data_width_lp data input port sel_i segments_p select port OUTPUT data_o data_width_lp data output port Assertion
None
Details & Circuit structure
pg_tree Releted Unit¶
bsg_pg_tree¶
Overview
This module builds a PG (propagate generate) tree.
Parameter
NAME DESCRIPTION DEFAULT input_width_p input data width “inv” output_width_p ouput data width “inv” nodes_p internal signal width 1 edges_lp internal signal width nodes_p*3 l_edge_p index value 0 r_edge_p index value 0 o_edge_p index value 0 node_TYPE_p index value 0 row_p index value 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT p_i input_width_p data input port g_i input_width_p data input port OUTPUT p_o output_width_p data output port g_o output_width_p data output port Assertion
None
Details & Circuit structure
Popcount Releted Uint¶
bsg_popcount¶
Overview
This module uses a recursive method to reduce the bit width of the input data.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT o log2(width_p+1) data output port Assertion
None
Details & Circuit structure
Reduce Releted Uint¶
bsg_reduce¶
Overview
The function of this module is to perform the reduction.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” xor_p xor operation judgment expression 0 and_p and operation judgment expression 0 or_p or operation judgment expression 0 harden_p use harden IP or not 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT o 1 data output port Assertion
None
Details & Circuit structure
bsg_reduce_segmented¶
Overview
The function of this module is to perform the segment_width_p bit reduction.
Parameter
NAME DESCRIPTION DEFAULT segments_p input and output data width. “inv” xor_p xor operation judgment expression 0 and_p and operation judgment expression 0 or_p or operation judgment expression 0 nor_p nor operation judgment expression 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT i segments_p*segment_width_p data input port OUTPUT o segments_p data output port Assertion
None
Details & Circuit structure
Rotate Shift Releted Unit¶
bsg_rotate_left¶
Overview
This is a left shift.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. -1
Port
TYPE NAME WIDTH DESCRIPTION INPUT data_i width_p data input port rot_i `BSG_SAFE_CLOG2(width_p) data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_rotate_right¶
Overview
This is a right shift.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. -1
Port
TYPE NAME WIDTH DESCRIPTION INPUT data_i width_p data input port rot_i `BSG_SAFE_CLOG2(width_p) data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
scan¶
bsg_scan¶
Overview
This module can encode the input data by selecting different modes.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. -1 xor_p control signal 0 and_p control signal 0 or_p control signal 0 lo_to_hi_p control signal 0 debug_p control signal 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
Cyclically Arbitration¶
bsg_strobe¶
Overview
The function of this module is to cyclically schedule arbitration.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT clk_i 1 data input port reset_r_i 1 data input port init_val_r_i width_p data input port OUTPUT strobe_r_o 1 data output port Assertion
None
Details & Circuit structure
Swap Unit¶
bsg_swap¶
Overview
The cell provides three ports(data_i,swap_i,data_o).The function of this module is to exchange the first row and the second row of the input array and output the position.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT data_i width_p data input port swap_i 1 control port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
Edge Detection Unit¶
bsg_thermometer_count¶
Overview
This module encodes and outputs the input data edge detection.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. -1
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT o $clog2(width_p+1) data output port Assertion
None
Details & Circuit structure
Output Fixed Bit Value Unit¶
bsg_tiehi¶
Overview
The function of this module is to output width_p bit 1.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_tielo¶
Overview
The function of this module is to output width_p bit 0.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
Output Switching Position Unit¶
bsg_transpose¶
Overview
The function of this module is to exchange the position of the bit width and the bit width of the input data for the output.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” els_p input and output data width. “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT i els_p*width_p data input port OUTPUT o els_p*width_p data output port Assertion
None
Details & Circuit structure
Unconcentrate Uint¶
bsg_unconcentrate_static¶
Overview
The function of this module is to extend the elements of the input vector according to the bit pattern.
Parameter
NAME DESCRIPTION DEFAULT width_p input data width. `BSG_COUNTONES_SYNTH(pattern_els_p) pattern_els_p output data width. “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_1p data input port OUTPUT o $bits(pattern_els_p) data output port Assertion
None
Details & Circuit structure
Reset Unit¶
bsg_wait_after_reset¶
Overview
The function of this module is to wait a certain number of cycles after reset to begin.
Parameter
NAME DESCRIPTION DEFAULT lg_wait_cycles_p register variable bit width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT reset_i 1 clk input port clk_i 1 reset input port OUTPUT ready_r_o 1 data output port Assertion
None
Details & Circuit structure
Wait Cycles Unit¶
bsg_wait_cycles¶
Overview
The function of this module is to wait for several cycles before the circuit starts to work.
Parameter
NAME DESCRIPTION DEFAULT cycles_p circuit intermediate variable bit width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT reset_i 1 clk input port clk_i 1 reset input port activate_i 1 data input port OUTPUT ready_r_o 1 data output port Assertion
None
Details & Circuit structure
