bsg_dataflow¶

tag¶

bsg_1_to_n_tagged¶

Overview

This module is intended to take one input and send it to one of several channels according to tag.
Parameter

NAME DESCRIPTION DEFAULT

num_out_p input and output data width -1

tag_width_lp input data width `BSG_SAFE_CLOG2(num_out_p)

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock port
RESET	reset_i	1	reset port
INPUT	v_i	width_p	data input port
	tag_i	tag_width_lp	data input port
	ready_i	num_out_p	data input port
OUTPUT	yumi_o	1	data output port
OUTPUT	v_o	num_out_p	data output port

Assertion

None

Details & Circuit structure

bsg_1_to_n_tagged_fifo¶

Overview

This module implements a FIFO that takes in a multiplexed stream on one end, and provides demultiplexed access on the other.

Parameter

NAME	DESCRIPTION	DEFAULT
width_p	input and output data width	“inv”
num_out_p	input data width	-1
els_p	input data width	“inv”
unbuffered_mask_p	input data width	0
use_pseudo_large_fifo_p	input data width	0
tag_width_lp	input data width	`BSG_SAFE_CLOG2(num_out_p)

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock port
RESET	reset_i	1	reset port
INPUT	v_i	1	data input port
	tag_i	tag_width_lp	data input port
	data_i	width_p	data input port
	yumi_i	num_out_p	data input port
OUTPUT	yumi_o	1	data output port
	v_o	num_out_p	data output port
	data_o	num_out_p*width_p	data output port

Assertion

None

Details & Circuit structure

bsg_1_to_n_tagged_fifo_shared¶

Overview

This module implements a FIFO that takes in a multiplexed stream on one end, and provides demultiplexed access on the other.

Parameter

NAME	DESCRIPTION	DEFAULT
width_p	input and output data width	“inv”
num_out_p	input data width	-1
els_p	input data width	“inv”
unbuffered_mask_p	input data width	0
use_pseudo_large_fifo_p	input data width	0
tag_width_lp	input data width	`BSG_SAFE_CLOG2(num_out_p)

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock port
RESET	reset_i	1	reset port
INPUT	v_i	1	data input port
	tag_i	tag_width_lp	data input port
	data_i	width_p	data input port
	yumi_i	num_out_p	data input port
OUTPUT	yumi_o	1	data output port
	v_o	num_out_p	data output port
	data_o	num_out_p*width_p	data output port

Assertion

None

Details & Circuit structure

Decode Releted Unit¶

bsg_8b10b_decode_comb¶

Overview

This module is byte oriented DC balanced 8B/10B block transfer decoder.
Parameter

None

Port

TYPE	NAME	WIDTH	DESCRIPTION
INPUT	data_i	10	data input port
INPUT	rd_i	1	data input port
OUTPUT	data_o	8	data output port
	k_o	1	data output port
	rd_o	1	data output port
	data_err_o	1	data output port
	rd_err_o	1	data output port

Assertion

None

Details & Circuit structure

bsg_8b10b_encode_comb¶

Overview

This module is byte oriented DC balanced 8B/10B block transfer encoder.
Parameter

None

Port

TYPE	NAME	WIDTH	DESCRIPTION
INPUT	data_i	8	data input port
	k_i	1	data input port
	rd_i	1	data input port
OUTPUT	data_o	10	data output port
	rd_o	1	data output port
	kerr_o	1	data output port

Assertion

None

Details & Circuit structure

bsg_8b10b_shift_decoder¶

Overview

This module is byte oriented DC balanced 8B/10B block transfer decoder with shift register.
Parameter

None

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clock	1	clock input port
INPUT	data_i	1	data input port
OUTPUT	data_o	8	data output port
	k_o	1	data output port
	v_o	1	data output port
	frame_align_o	1	data output port

Assertion

None

Details & Circuit structure

Channel Narrow Unit¶

bsg_channel_narrow¶

Overview

This module takes output of a previous module and sends this data in smaller number of bits by receiving deque from next module.
Parameter

NAME DESCRIPTION DEFAULT

width_in_p input data width -1

width_out_p output data width -1

lsb_to_msb_p select signal 1

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clock	1	clock input port
RESET	reset_i	1	reset input port
INPUT	data_i	width_in_p	data input port
INPUT	deque_i	1	data input port
OUTPUT	deque_o	1	data output port
OUTPUT	data_o	1width_out_p	data output port

Assertion

None

Details & Circuit structure

bsg_channel_narrow¶

Overview

This module takes output of a previous module and sends this data in smaller number of bits by receiving deque from next module.
Parameter

NAME DESCRIPTION DEFAULT

width_in_p input data width -1

width_out_p output data width -1

lsb_to_msb_p select signal 1

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clock	1	clock input port
RESET	reset_i	1	reset input port
INPUT	data_i	width_in_p	data input port
INPUT	deque_i	1	data input port
OUTPUT	deque_o	1	data output port
OUTPUT	data_o	1width_out_p	data output port

Assertion

None

Details & Circuit structure

Channel Tunnel Releted Unit¶

bsg_channel_tunnel¶

Overview

This module allows you to multiplex multiple streams over a shared interconnect without having deadlock occur because of stream interleaving.

Parameter

NAME	DESCRIPTION	DEFAULT
width_p	input and output data width	1
num_in_p	input and output data width	“inv”
remote_credits_p	input data width	“inv”
use_pseudo_large_fifo_p	input data width	0
lg_remote_credits_lp	internal signal width	$clog2(remote_credits_p+1)
lg_credit_decimation_p	input data width	`BSG_MIN(lg_remote_credits_lp,4)
tag_width_lp	input data width	$clog2(num_in_p+1)
tagged_width_lp	input data width	tag_width_lp + width_p

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clock	1	clock input port
RESET	reset_i	1	reset input port
INPUT	multi_data_i	tagged_width_lp	data input port
	multi_v_i	1	data input port
	multi_yumi_i	1	data input port
	data_i	num_in_p*width_p	data input port
	v_i	num_in_p	data input port
	yumi_i	num_in_p	data input port
OUTPUT	multi_yumi_o	1	data output port
	multi_data_o	tagged_width_lp	data output port
	multi_v_o	1	data output port
	yumi_o	num_in_p	data output port
	data_o	num_in_p*width_p	data output port
	v_o	num_in_p	data output port

Assertion

None

Details & Circuit structure

bsg_channel_tunnel_in¶

Overview

This module takes N channels and tunnels them, with credit flow control.

Parameter

NAME	DESCRIPTION	DEFAULT
width_p	input and output data width	-1
num_in_p	input and output data width	“inv”
remote_credits_p	input data width	“inv”
use_pseudo_large_fifo_p	input data width	0
lg_remote_credits_lp	internal signal width	$clog2(remote_credits_p+1)
lg_credit_decimation_p	input data width	4
tag_width_lp	input data width	$clog2(num_in_p+1)
tagged_width_lp	input data width	tag_width_lp+width_p

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clock	1	clock input port
RESET	reset_i	1	reset input port
INPUT	data_i	tagged_width_lp	data input port
	v_i	1	data input port
	yumi_i	num_in_p	data input port
OUTPUT	yumi_o	1	data output port
	data_o	num_in_p*width_p	data output port
	v_o	num_in_p	data output port
	credit_local_return_data_o	num_in_p*lg_remote_credits_lp	data output port
	credit_local_return_v_o	num_in_p*width_p	data output port

Assertion

None

Details & Circuit structure

bsg_channel_tunnel_out¶

Overview

This module takes N channels and tunnels them, with credit flow control.

Parameter

NAME	DESCRIPTION	DEFAULT
width_p	input and output data width	-1
num_in_p	input and output data width	“inv”
remote_credits_p	input data width	“inv”
lg_remote_credits_lp	internal signal width	$clog2(remote_credits_p+1)
lg_credit_decimation_p	input data width	4
tag_width_lp	input data width	$clog2(num_in_p+1)
tagged_width_lp	input data width	tag_width_lp+width_p

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clock	1	clock input port
RESET	reset_i	1	reset input port
INPUT	data_i	num_in_p*width_p	data input port
	v_i	num_in_p	data input port
	yumi_i	1	data input port
	credit_local_return_data_i	1	data output port
	credit_local_return_v_i	1	data output port
	credit_remote_return_data_i	1	data output port
OUTPUT	yumi_o	num_in_p	data output port
	data_o	tagged_width_lp	data output port
	v_o	1	data output port
	credit_remote_return_yumi_o	1	data output port

Assertion

None

Details & Circuit structure

bsg_channel_tunnel_wormhole¶

Overview

This module is a special version bsg_channel_tunnel that accepts wormhole packet.

Parameter

NAME	DESCRIPTION	DEFAULT
width_p	input and output data width	“inv”
x_cord_width_p	data width	“inv”
y_cord_width_p	data width	“inv”
len_width_p	length width	“inv”
reserved_width_p	data width	“inv”
num_in_p	total number of inputs multiplexed	“inv”
remote_credits_p	max number of wormhole packets buffer can store	“inv”
max_payload_flits_p	max possible “wormhole packet payload length” setting	“inv”
lg_credit_decimation_p	how often does channel tunnel return credits to sender	`BSG_MIN($clog2(remote_credits_p+1),4)
use_pseudo_large_fifo_p	use pseudo large fifo when read / write utilization is less than 50%	1
bsg_ready_and_link_sif_width_lp	local parameters	`bsg_ready_and_link_sif_width(width_p)

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clock	1	clock input port
RESET	reset_i	1	reset input port
INPUT	multi_data_i	width_p	data input port
	multi_v_i	1	data input port
	multi_yumi_i	1	data input port
	link_i	num_in_p*bsg_ready_and_link_sif_width_lp	data input port
OUTPUT	multi_ready_o	1	data output port
	multi_data_o	width_p	data output port
	multi_v_o	1	data output port
	link_o	num_in_p*bsg_ready_and_link_sif_width_lp	data output port

Assertion

None

Details & Circuit structure

Compare Swap Releted Unit¶

bsg_compare_and_swap¶

Overview

This module compare two values and swap them if they are not in order.

Parameter

NAME	DESCRIPTION	DEFAULT
width_p	input and output data width	“inv”
t_p	data range	`BSG_SAFE_CLOG2(num_out_p)
b_p	data range	`BSG_SAFE_CLOG2(num_out_p)
cond_swap_on_equal_p	select signal	`BSG_SAFE_CLOG2(num_out_p)

Port

TYPE NAME WIDTH DESCRIPTION

INPUT data_i 2*width_p data input port

swap_on_equal_i 1 data input port

OUTPUT data_o 2*width_p data output port

swapped_o 1 data output port
Assertion

None

Details & Circuit structure

Counter Releted Unit¶

bsg_credit_to_token¶

Overview

This module is a counter for credits, that every decimation_p credits it would assert token_o signal once.
Parameter

NAME DESCRIPTION DEFAULT

decimation_p signal width -1

max_val_p signal width -1

Port

TYPE NAME WIDTH DESCRIPTION

CLOCK clk_i 1 clock input port

RESET reset_i 1 reset input port

INPUT credit_i 1 data input port

ready_i 1 data input port

OUTPUT token_o 1 data output port
Assertion

None

Details & Circuit structure

RAM Releted Unit¶

bsg_fifo_1r1w_large¶

Overview

This implementation is specifically intended for processes where 1RW rams are much cheaper than 1R1W rams.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width -1

els_p internal signal width -1

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	data_i	width_p	data input port
	v_i	1	data input port
	yumi_i	1	data input port
OUTPUT	ready_o	1	data output port
	v_o	1	data output port
	data_o	width_p	data output port

Assertion

None

Details & Circuit structure

bsg_fifo_1r1w_large_banked¶

Overview

This implementation using two banks is specifically intended for processes where 1RW rams are much cheaper than 1R1W rams.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width -1

els_p internal signal width -1

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	data_i	width_p	data input port
	v_i	1	data input port
	yumi_i	1	data input port
OUTPUT	ready_o	1	data output port
	v_o	1	data output port
	data_o	width_p	data output port

Assertion

None

Details & Circuit structure

bsg_fifo_1r1w_narrowed¶

Overview

This module is a small fifo which has a bsg_channel_narrow on its output, that would send out each data in several steps based on the input and output width.
Parameter

NAME DESCRIPTION DEFAULT

width_p input data width -1

els_p internal signal width -1

width_out_p output data width -1

lsb_to_msb_p select signal -1

ready_THEN_valid_p select signal 0

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	data_i	width_p	data input port
	v_i	1	data input port
	yumi_i	1	data input port
OUTPUT	ready_o	1	data output port
	v_o	1	data output port
	data_o	width_out_p	data output port

Assertion

None

Details & Circuit structure

bsg_fifo_1r1w_pseudo_large¶

Overview

This fifo looks like a 1R1W fifo but actually is implemented with a 1RW FIFO for the bulk of its storage, and has a small 1R1W FIFO to help decouple reads and writes that may conflict.
Parameter

NAME DESCRIPTION DEFAULT

width_p input data width -1

els_p internal signal width -1

early_yumi_p select signal 1

verbose_p select signal 0

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	data_i	width_p	data input port
	v_i	1	data input port
	yumi_i	1	data input port
OUTPUT	ready_o	1	data output port
	v_o	1	data output port
	data_o	width_p	data output port

Assertion

None

Details & Circuit structure

bsg_fifo_1r1w_small¶

Overview

This module implements a FIFO with 1 read and 1 write and can use different memory implementations.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width -1

els_p internal signal width -1

harden_p use harden IP or not 0

ready_THEN_valid_p select signal 0

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	data_i	width_p	data input port
	v_i	1	data input port
	yumi_i	1	data input port
OUTPUT	ready_o	1	data output port
	v_o	1	data output port
	data_o	width_p	data output port

Assertion

None

Details & Circuit structure

bsg_fifo_1r1w_small_credit_on_input¶

Overview

This module converts between the valid-credit (input) and valid-ready (output) handshakes, by using a fifo to keep the data.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width -1

els_p internal signal width -1

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	data_i	width_p	data input port
	v_i	1	data input port
	yumi_i	1	data input port
OUTPUT	credit_o	1	data output port
	v_o	1	data output port
	data_o	width_p	data output port

Assertion

None

Details & Circuit structure

bsg_fifo_1r1w_small_hardened¶

Overview

This module is a FIFO with 1 read and 1 write,used for smaller FIFOs.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width -1

els_p internal signal width -1

ready_THEN_valid_p select signal 0

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	data_i	width_p	data input port
	v_i	1	data input port
	yumi_i	1	data input port
OUTPUT	ready_o	1	data output port
	v_o	1	data output port
	data_o	width_p	data output port

Assertion

None

Details & Circuit structure

bsg_fifo_1r1w_small_unhardened¶

Overview

This module is a FIFO with 1 read and 1 write,using 1-write 1-async-read resgister file implementation.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width -1

els_p internal signal width -1

ready_THEN_valid_p select signal 0

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	data_i	width_p	data input port
	v_i	1	data input port
	yumi_i	1	data input port
OUTPUT	ready_o	1	data output port
	v_o	1	data output port
	data_o	width_p	data output port

Assertion

None

Details & Circuit structure

bsg_fifo_1rw_large¶

Overview

This module is a FIFO with only one read or write port, using a 1RW synchronous read ram.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width -1

els_p internal signal width -1

verbose_p select signal 0

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	data_i	width_p	data input port
	v_i	1	data input port
	enq_not_deq_i	1	data input port
OUTPUT	full_o	1	data output port
	empty_o	1	data output port
	data_o	width_p	data output port

Assertion

None

Details & Circuit structure

bsg_fifo_bypass¶

Overview

This module is a FIFO bypass circuit.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width “inv”

ready_THEN_valid_p select signal 0

Port

TYPE	NAME	WIDTH	DESCRIPTION
INPUT	data_i	width_p	data input port
	v_i	1	data input port
	yumi_i	1	data input port
	fifo_ready_i	width_p	data input port
	fifo_data_i	width_p	data input port
	fifo_v_i	1	data input port
OUTPUT	ready_o	1	data output port
	data_o	width_p	data output port
	v_o	1	data output port
	fifo_data_o	width_p	data output port
	fifo_v_o	1	data output port
	fifo_yumi_o	1	data output port

Assertion

None

Details & Circuit structure

bsg_fifo_reorder¶

Overview

This module is a reordering circuit for FIFO.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width “inv”

els_p Internal signal range “inv”

lg_els_lp input and output data width `BSG_SAFE_CLOG2(els_p)

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	fifo_alloc_yumi_i	1	data input port
	write_v_i	1	data input port
	write_id_i	1	data input port
	write_data_i	width_p	data input port
	fifo_deq_yumi_i	1	data input port
OUTPUT	fifo_alloc_v_o	1	data output port
	fifo_alloc_id_o	lg_els_lp	data output port
	fifo_deq_v_o	1	data output port
	fifo_deq_data_o	width_p	data output port
	empty_o	1	data output port

Assertion

None

Details & Circuit structure

bsg_fifo_shift_datapath¶

Overview

This module creates an array of shift registers, with independently controlled three input muxes.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width “inv”

els_p input data width “inv”

default_p default initial value { (width_p) {1’b0} }

Port

TYPE NAME WIDTH DESCRIPTION

CLOCK clk_i 1 clock input port

INPUT data_i width_p data input port

sel_i els_p*2 data input port

OUTPUT data_o width_p data output port
Assertion

None

Details & Circuit structure

bsg_fifo_tracker¶

Overview

This module returns whether FIFO is empty or full.
Parameter

NAME DESCRIPTION DEFAULT

els_p input and output data width -1

ptr_width_lp input and output data width `BSG_SAFE_CLOG2(els_p)

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	enq_i	1	data input port
INPUT	deq_i	1	data input port
OUTPUT	wptr_r_o	ptr_width_lp	data output port
	rptr_r_o	ptr_width_lp	data output port
	rptr_n_o	ptr_width_lp	data output port
	full_o	1	data output port
	empty_o	1	data output port

Assertion

None

Details & Circuit structure

bsg_flatten_2D_array¶

Overview

This module converts a two-dimensional array to a one-dimensional array.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width -1

items_p input and output data width -1

Port

TYPE NAME WIDTH DESCRIPTION

INPUT i width_p*items_p data input port

OUTPUT o width_p*items_p data output port
Assertion

None

Details & Circuit structure

bsg_flow_convert¶

Overview

This module converts between the various link-level flow-control protocols.

Parameter

NAME	DESCRIPTION	DEFAULT
send_v_and_ready_p	input data width	0
send_v_then_yumi_p	select signal	0
send_ready_then_v_p	select signal	0
send_retry_then_v_p	select signal	0
send_v_and_retry_p	select signal	0
recv_v_and_ready_p	select signal	0
recv_v_then_yumi_p	select signal	0
recv_ready_then_v_p	select signal	0
recv_v_and_retry_p	select signal	0
recv_v_then_retry_p	select signal	0
width_p	input and output data width	1

Port

TYPE NAME WIDTH DESCRIPTION

INPUT v_i width_p data input port

fc_i width_p data input port

OUTPUT fc_o width_p data output port

v_o width_p data output port
Assertion

None

Details & Circuit structure

bsg_flow_counter¶

Overview

This module counts the number of free elements or number of existing elements in the connected module.
Parameter

NAME DESCRIPTION DEFAULT

els_p output data width -1

count_free_p select signal 0

ready_THEN_valid_p select signal 0

ptr_width_lp output data width `BSG_WIDTH(els_p)

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	v_i	1	data input port
	ready_i	1	data input port
	yumi_i	1	data input port
OUTPUT	count_o	ptr_width_lp	data output port

Assertion

None

Details & Circuit structure

bsg_make_2D_array¶

Overview

This module creates a two-dimensional array.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width -1

items_p input and output data width -1

Port

TYPE NAME WIDTH DESCRIPTION

INPUT i width_p*items_p data input port

OUTPUT o width_p*items_p data output port
Assertion

None

Details & Circuit structure

bsg_one_fifo¶

Overview

This module is used to pipeline links and convert interfaces from valid/ready to valid->yumi.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width “inv”

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	data_i	width_p	data input port
	v_i	1	data input port
	yumi_i	1	data input port
OUTPUT	ready_o	1	data output port
	v_o	1	data output port
	data_o	ptr_width_lp	data output port

Assertion

None

Details & Circuit structure

parallel in serial out¶

bsg_parallel_in_serial_out¶

Overview

This module takes in a multi-word data and serializes it to a single word output.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width -1

els_p input data width -1

hi_to_lo_p select signal 0

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	data_i	els_p*width_p	data input port
	valid_i	1	data input port
	yumi_i	1	data input port
OUTPUT	ready_o	1	data output port
	valid_o	1	data output port
	data_o	width_p	data output port

Assertion

None

Details & Circuit structure

bsg_parallel_in_serial_out_dynamic¶

Overview

This module takes in a multi-word data and serializes it to a single word output.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width “inv”

max_els_p input data width “inv”

lg_max_els_lp input data width `BSG_SAFE_CLOG2(max_els_p)

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	v_i	1	data input port
	len_i	lg_max_els_lp	data input port
	data_i	max_els_p*width_p	data input port
	yumi_i	1	data input port
OUTPUT	ready_o	1	data output port
	v_o	1	data output port
	len_v_o	1	data output port
	data_o	width_p	data output port

Assertion

None

Details & Circuit structure

selector¶

bsg_permute_box¶

Overview

This module selects the input signal and outputs it.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width “inv”

items_p input and output data width “inv”

lg_items_lp input data width $bits(items_p)

Port

TYPE NAME WIDTH DESCRIPTION

INPUT data_i width_p*items_p data input port

select_i lg_items_lp*items_p data input port

OUTPUT data_o width_p*items_p data output port
Assertion

None

Details & Circuit structure

converter¶

bsg_ready_to_credit_flow_converter¶

Overview

This module converts between the valid-ready (input) and valid-credit (output) handshakes, by keeping the count of available credits.

Parameter

NAME	DESCRIPTION	DEFAULT
credit_initial_p	input and output data width	-1
credit_max_val_p	input data width	-1
decimation_p	select signal	1
ptr_width_lp	internal signal bit width	`BSG_WIDTH(credit_max_val_p)

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	v_i	1	data input port
INPUT	credit_i	1	data input port
OUTPUT	ready_o	1	data output port
OUTPUT	v_o	1	data output port

Assertion

None

Details & Circuit structure

bsg_relay_fifo¶

Overview

This module converts between the valid-ready (input) and valid-credit (output) handshakes, by keeping the count of available credits.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width “inv”

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	data_i	width_p	data input port
	v_i	1	data input port
	ready_i	1	data input port
OUTPUT	ready_o	1	data output port
	v_o	1	data output port
	data_o	width_p	data output port

Assertion

None

Details & Circuit structure

Round Robin Releted Unit¶

bsg_round_robin_1_to_n¶

Overview

This module is intended to take one input and send it to one of several channels in round robin order.
Parameter

NAME DESCRIPTION DEFAULT

width_p useless “inv”

num_out_p input and output data width 2

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	valid_i	1	data input port
INPUT	ready_i	num_out_p	data input port
OUTPUT	ready_o	1	data output port
OUTPUT	valid_o	num_out_p	data output port

Assertion

None

Details & Circuit structure

bsg_round_robin_2_to_2¶

Overview

This module is intended for round robining on the input to a pair of fifos.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width “inv”

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	data_i	width_p*2	data input port
	v_i	2	data input port
	ready_i	2	data input port
OUTPUT	ready_o	2	data output port
	data_o	width_p*2	data output port
	v_o	2	data output port

Assertion

None

Details & Circuit structure

bsg_rr_f2f_input¶

Overview

This module is intended for round robining on the input to a pair of fifos.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width “inv”

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	data_i	width_p*2	data input port
	v_i	2	data input port
	ready_i	2	data input port
OUTPUT	ready_o	2	data output port
	data_o	width_p*2	data output port
	v_o	2	data output port

Assertion

None

Details & Circuit structure

bsg_round_robin_n_to_1¶

Overview

This module is intended to merge the outputs of several fifos together to act as one.

Parameter

NAME	DESCRIPTION	DEFAULT
width_p	input and output data width	-1
num_in_p	input and output data width	-1
strict_p	select signal	“inv”
tag_width_lp	output data width	`BSG_SAFE_CLOG2(num_in_p)

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	data_i	num_in_p*width_p	data input port
	v_i	num_in_p	data input port
	yumi_i	1	data input port
OUTPUT	yumi_o	num_in_p	data output port
	v_o	1	data output port
	data_o	width_p	data output port
	tag_o	tag_width_lp	data output port

Assertion

None

Details & Circuit structure

sbox¶

bsg_sbox¶

Overview

This module concentrates working channel signals to reduce the complexity of downstream logic.

Parameter

NAME	DESCRIPTION	DEFAULT
num_channels_p	input and output data width	“inv”
channel_width_p	input and output data width	“inv”
pipeline_indir_p	select signal	“inv”
pipeline_outdir_p	select signal	0
one_hot_p	select signal	1

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	calibration_done_i	1	data input port
	channel_active_i	num_channels_p	data input port
	in_v_i	num_channels_p	data input port
	in_data_i	channel_width_p*num_channels_p	data input port
	out_me_v_i	num_in_p*width_p	data input port
	out_me_data_i	num_in_p	data input port
	out_me_ready_i	1	data input port
	in_yumi_i	1	data input port
OUTPUT	in_yumi_o	num_channels_p	data output port
	in_v_o	num_channels_p	data output port
	in_data_o	channel_width_p*num_channels_p	data output port
	out_me_ready_o	num_channels_p	data output port
	out_me_v_o	num_channels_p	data output port
	out_me_data_o	channel_width_p*num_channels_p	data output port

Assertion

None

Details & Circuit structure

bsg_sbox_ctrl_concentrate¶

Overview

This module generates permutation vectors that perform concentration (fwd) and deconcentration (bkwd).
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width -1

lg_width_p output data width -1

Port

TYPE	NAME	WIDTH	DESCRIPTION
INPUT	vec_i	width_p	data input port
OUTPUT	fwd_perm_o	lg_width_p*width_p	data output port
	fwd_valid_o	width_p	data output port
	bkwd_perm_o	lg_width_p*width_p	data output port

Assertion

None

Details & Circuit structure

Vectors Releted Unit¶

bsg_scatter_gather¶

Overview

This module generates permutation vectors that perform concentration (fwd) and deconcentration (bkwd).
Parameter

NAME DESCRIPTION DEFAULT

vec_size_lp input and output data width “inv”

Port

TYPE	NAME	WIDTH	DESCRIPTION
INPUT	vec_i	width_p	data input port
OUTPUT	fwd_o	lg_width_p*width_p	data output port
	fwd_datapath_o	width_p	data output port
	bk_o	lg_width_p*width_p	data output port
	bk_datapath_o	lg_width_p*width_p	data output port

Assertion

None

Details & Circuit structure

data structure¶

bsg_serial_in_parallel_out¶

Overview

This module is a data structure that takes one word per cycle and allows more than one word per cycle to exit and the number of words extracted can vary dynamically.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width -1

els_p internal initial signal bit width -1

out_els_p input and output data width els_p

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	valid_i	1	data input port
	data_i	width_p	data input port
	yumi_cnt_i	$clog2(out_els_p+1)	data input port
OUTPUT	ready_o	1	data output port
	valid_o	out_els_p	data output port
	data_o	out_els_p*width_p	data output port

Assertion

None

Details & Circuit structure

bsg_serial_in_parallel_out_dynamic¶

Overview

This module is a data structure that takes one word per cycle and allows more than one word per cycle to exit and the number of words extracted can vary dynamically.

Parameter

NAME	DESCRIPTION	DEFAULT
width_p	input and output data width	“inv”
max_els_p	internal initial signal bit width	“inv”
lg_max_els_lp	input and output data width	`BSG_SAFE_CLOG2(max_els_p)

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	v_i	1	data input port
	len_i	width_p	data input port
	data_i	$clog2(out_els_p+1)	data input port
	yumi_i	1	data input port
OUTPUT	ready_o	1	data output port
	len_ready_o	1	data output port
	v_o	1	data output port
	data_o	max_els_p*width_p	data output port

Assertion

None

Details & Circuit structure

bsg_serial_in_parallel_out_full¶

Overview

This module is a simpler version of bsg_serial_in_parallel_out.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width “inv”

els_p output data width “inv”

hi_to_lo_p select signal 0

use_minimal_buffering_p select signal 0

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	v_i	1	data input port
	data_i	width_p	data input port
	yumi_i	1	data input port
OUTPUT	ready_o	1	data output port
	data_o	els_p*width_p	data output port
	v_o	1	data output port

Assertion

None

Details & Circuit structure

Shift Register Releted Unit¶

bsg_shift_reg¶

Overview

This module implements a shift register of fixed latency.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width “inv”

stages_p internal initial signal bit width “inv”

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	valid_i	1	data input port
INPUT	data_i	width_p	data input port
OUTPUT	valid_o	1	data output port
OUTPUT	data_o	width_p	data output port

Assertion

None

Details & Circuit structure

Sort Network Releted Unit¶

bsg_sort_4¶

Overview

This module is a sorting network implementation.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width “inv”

items_p input and output data width 4

t_p inclusive range of bits width_p-1

b_p inclusive range of bits 0

Port

TYPE NAME WIDTH DESCRIPTION

INPUT i width_p*items_p data input port

OUTPUT o width_p*items_p data output port
Assertion

None

Details & Circuit structure

bsg_sort_stable¶

Overview

This module implements a stable 4-item sort.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width “inv”

items_p input and output data width 4

t_p inclusive range of bits width_p-1

b_p inclusive range of bits 0

Port

TYPE NAME WIDTH DESCRIPTION

INPUT i width_p*items_p data input port

OUTPUT o width_p*items_p data output port
Assertion

None

Details & Circuit structure

two buncher¶

bsg_two_buncher¶

Overview

This module takes an incoming stream of words. if the output is read every cycle, the data passes straight through without latency. if the output is not read, then one element is buffered internally and either one or two elements may be pulled out on the next cycle.
Parameter

NAME DESCRIPTION DEFAULT

width_p input and output data width -1

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	data_i	1	data input port
	v_i	width_p	data input port
	ready_i	width_p	data input port
OUTPUT	ready_o	1	data output port
	data_o	2*width_p	data output port
	v_o	2	data output port

Assertion

None

Details & Circuit structure

Two FIFO¶

bsg_two_fifo¶

Overview

This module implements two element FIFO.

Parameter

NAME	DESCRIPTION	DEFAULT
width_p	input and output data width	“inv”
verbose_p	select signal	0
allow_enq_deq_on_full_p	select signal	0
ready_THEN_valid_p	select signal	allow_enq_deq_on_full_p

Port

TYPE	NAME	WIDTH	DESCRIPTION
CLOCK	clk_i	1	clock input port
RESET	reset_i	1	reset input port
INPUT	v_i	1	data input port
INPUT	yumi_i	1	data input port
OUTPUT	ready_o	1	data output port
	data_o	width_p	data output port
	v_o	1	data output port

Assertion

None

Details & Circuit structure