bsg_misc¶
Multiplier Releted Unint¶
bsg_mul_comp42¶
Overview
This module is a adder for mul.
Parameter
None
Port
TYPE NAME WIDTH DESCRIPTION INPUT i 4 data input port cr_i 1 data input port OUTPUT cl_o 1 data output port c_o 1 data output port s_o 1 data output port Assertion
None
Details & Circuit structure
bsg_mul_comp42_rep¶
Overview
This module combine vectors of results from blocks.
Parameter
NAME DESCRIPTION DEFAULT blocks_p signal width 1 harden_p use harden IP or not 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT i 4*blocks_p data input port cr_i 1 data input port OUTPUT cl_o 1 data output port c_o blocks_p data output port s_o blocks_p data output port Assertion
None
Details & Circuit structure
bsg_mul_booth_4_block¶
Overview
This module is a block of mul_booth_4.
Parameter
NAME DESCRIPTION DEFAULT S_above_vec_p select signal 4’b0000 dot_bar_vec_p select signal 4’b0000 B_vec_p select signal 4’b0000 one_vec_p select signal 4’b0000
Port
TYPE NAME WIDTH DESCRIPTION INPUT SDN_i 15 data input port cr_i 1 data input port y_i 8 data input port OUTPUT cl_o 1 data output port c_o 1 data output port s_o 1 data output port Assertion
None
Details & Circuit structure
bsg_mul_booth_4_block_rep¶
Overview
This module combine vectors of results from blocks.
Parameter
NAME DESCRIPTION DEFAULT blocks_p input and output data width 1 S_above_vec_p select signal 0 dot_bar_vec_p select signal 0 B_vec_p select signal 0 one_vec_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT SDN_i 15 data input port cr_i 1 data input port y_vec_i 8*blocks_p data input port OUTPUT cl_o 1 data output port c_o blocks_p data output port s_o blocks_p data output port Assertion
None
Details & Circuit structure
bsg_imul_iterative¶
Overview
This is an 32bit integer iterative multiplier, capable of signed & unsigned multiplication.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width 32
Port
Assertion
None
Details & Circuit structure
bsg_mul_array¶
Overview
This module is a pipelined unsigned array multiplier.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” pipeline_p selcet signal 1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET rst_i 1 reset input port INPUT v_i 1 data input port a_i width_p data input port b_i width_p data input port OUTPUT o 2*width_p data output port Assertion
None
Details & Circuit structure
bsg_mul_array_row¶
Overview
This module is a pipelined adder.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” row_idx_p input and output data width “inv” pipeline_p selcet signal “inv”
Port
Assertion
None
Details & Circuit structure
bsg_mul_pipelined¶
Overview
This is a library of multipliers.
bsg_mul_synth¶
Overview
This is synthesized multiplier.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port b_i width_p data input port OUTPUT o 2*width_p data output port Assertion
None
Details & Circuit structure
bsg_mul¶
Overview
This module is a pipeline multiplier.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT x_i width_p data input port y_i width_p data input port signed_i 1 data input port OUTPUT z_o width_p data output port Assertion
None
Details & Circuit structure
Logic Gate Releted Unit¶
bsg_abs¶
Overview
This module calculates the absolute value of signed integers.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port OUTPUT a_o width_p data output port Assertion
None
Details & Circuit structure
bsg_and¶
Overview
This is a two-input AND gate.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port b_i width_p data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_inv¶
Overview
This is an inverter.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_nand¶
Overview
This is a two-input NAND gate.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port b_i width_p data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_nor2¶
Overview
This is a two-input NOR gate.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port b_i width_p data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_nor3¶
Overview
This is a three-input NOR gate.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port b_i width_p data input port c_i width_p data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_xnor¶
Overview
This is a two-input XNOR gate.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port b_i width_p data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_xor¶
Overview
This is a two-input XOR gate.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port b_i width_p data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
Adder Releted Unit¶
bsg_adder_cin¶
Overview
This module implements a simple adder with cin.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port b_i width_p data input port cin_i 1 data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_adder_one_hot¶
Overview
This module calculates the absolute value of signed integers.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port b_i width_p data input port OUTPUT o output_width_p data output port Assertion
assert (output_width_p >= width_p)
Details & Circuit structure
bsg_adder_ripple_carry¶
Overview
This is a traveling wave carry adder.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port b_i width_p data input port OUTPUT s_o width_p data output port c_o 1 data output port Assertion
None
Details & Circuit structure
Encoder Releted Unit¶
bsg_priority_encode¶
Overview
The function of this module is to encode and output the input data twice.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” lo_to_hi_p control signal “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT v_o 1 data output port addr_o `BSG_SAFE_CLOG2(width_p)-1 data output port Assertion
None
Details & Circuit structure
bsg_priority_encode_one_hot_out¶
Overview
This module encodes by one-hot and outputs the input data.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” lo_to_hi_p control signal “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT v_o 1 data output port o width_p data output port Assertion
None
Details & Circuit structure
bsg_arb_fixed¶
Overview
This is a priority encoder that can control the output to all 0 or the encoded result.
Parameter
NAME DESCRIPTION DEFAULT inputs_p input and output data width “inv” lo_to_hi_p control signal “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT ready_i 1 data input port reqs_i width_p data input port OUTPUT grants_0 width_p data output port Assertion
None
Details & Circuit structure
bsg_arb_round_robin¶
Overview
This is a circular encoder.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock port RESET reset_i 1 reset port INPUT reqs_i width_p data input port yumi_i 1 data input port OUTPUT grants_o width_p data output port Assertion
None
Details & Circuit structure
bsg_arrary_concentrate¶
Overview
This module outputs an input array of a certain number of digits.
Parameter
NAME DESCRIPTION DEFAULT pattern_els_p input and output data width “inv” width_p input and output data width “inv” dense_els_lp input data width $bits(pattern_els_p) sparse_els_lp output data width `BSG_COUNTONES_SYNTH(pattern_els_p)
Port
TYPE NAME WIDTH DESCRIPTION INPUT i dense_els_lp*width_p data input port OUTPUT o sparse_els_lp*width_p data output port Assertion
None
Details & Circuit structure
bsg_array_reverse¶
Overview
This module reverse the input array for output.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” els_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT i els_p*width_p data input port OUTPUT o els_p*width_p data output port Assertion
None
Details & Circuit structure
bsg_binary_plus_one_to_gray¶
Overview
This module converts binary input + 1 to gray code.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. -1
Port
TYPE NAME WIDTH DESCRIPTION INPUT binary_i width_p data input port OUTPUT gray_o width_p data output port Assertion
None
Details & Circuit structure
Buffer Releted Unit¶
bsg_buf¶
Overview
This is a buffer circuit.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_buf_ctrl¶
Overview
This module buff 1 bit control signal to width_p vector.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT i 1 data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_clkbuf¶
Overview
This module is a buffer.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. 1 harden_p use harden IP or not 1 strength_p no 8
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg¶
bsg_concentrate_static¶
Overview
This module given a bunch of signals, and a bitvector parameter,concentrate those bits together into a more condensed vector.
Parameter
NAME DESCRIPTION DEFAULT pattern_els_p input and output data width “inv” width_lp input data width $bits(pattern_els_p) set_els_lp output data width `BSG_COUNTONES_SYNTH(pattern_els_p)
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_lp data input port OUTPUT o set_els_lp data output port Assertion
None
Details & Circuit structure
bsg¶
bsg_circular_ptr¶
Overview
This module implements a circular pointer that can be incremented by at most max_add_p and points to slots_p slots.
Parameter
Name DESCRIPTION DEFAULT slots_p output data width -1 max_add_p input data width -1 ptr_width_lp output data width -1
Port
Type NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT add_i $clog2(max_add_p+1) data input port OUTPUT o ptr_width_lp data output port n_o ptr_width_lp data output port Assertion
None
Details & Circuit structure
bsg_clkgate_optional¶
Overview
This is an integrated clock cell using a negative latch and an AND gate.
Parameter
None
Port
Type NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port INPUT en_i 1 data input port bypass_i 1 data input port OUTPUT gated_clock_o 1 data output port Assertion
None
Details & Circuit structure
Counter Releted Unit¶
bsg_counter_clear_up¶
Overview
This counter counts up and is occasionally cleared.
Parameter
NAME DESCRIPTION DEFAULT max_val_p set the max value -1 init_val_p set the initial value of the count `BSG_UNDEFINED_IN_SIM(‘0) ptr_width_lp output data width `BSG_SAFE_CLOG2(max_val_p+1) disable_overflow_warning_p overflow signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port CLEAR clear_i 1 clear input port INPUT up_i 1 data input port OUTPUT count_o ptr_width_lp data output port Assertion
None
Details & Circuit structure
bsg_counter_clear_up_one_hot¶
Overview
This counter is a one hot counter only one output bit is set at any time.
Parameter
NAME DESCRIPTION DEFAULT max_val_p set the max value -1 init_val_p set the initial value of the count (width_lp) ‘ (1) width_lp output data width max_val_p+1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port CLEAR clear_i 1 clear input port INPUT up_i 1 data input port OUTPUT count_o width_lp data output port Assertion
None
Details & Circuit structure
bsg_counter_clock_downsample¶
Overview
This counter will counter down from val_i to 0.When the counter hits 0, the output clk_r_o will invert.
Parameter
NAME DESCRIPTION DEFAULT width_p input data width “inv” harden_p use harden IP or not 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT val_i width_p data input port OUTPUT clk_r_o 1 data output port Assertion
None
Details & Circuit structure
bsg_counter_dynamic_limit¶
Overview
This module is a counter with dynamic limit that repeats counting from zero to overflow value.
Parameter
NAME DESCRIPTION DEFAULT width_p input data width -1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT limit_i width_p data input port OUTPUT counter_o width_p data output port Assertion
None
Details & Circuit structure
bsg_counter_dynamic_limit_en¶
Overview
This module implements simple counter with enable signal and dynamic overflow limit.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT en_i 1 setting port limit_i width_p data input port OUTPUT counter_o width_p data output port overflowed_o 1 data output port Assertion
None
Details & Circuit structure
bsg_counter_overflow_en¶
Overview
This is a counter with an overflow flag bit.
Parameter
NAME DESCRIPTION DEFAULT max_val_p max value -1 init_val_p initial value -1 ptr_width_lp output data width `BSG_SAFE_CLOG2(max_val_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT en_i 1 setting port OUTPUT count_o ptr_width_lp data output port overflow_o 1 data output port Assertion
None
Details & Circuit structure
bsg_counter_overflow_set_en¶
Overview
This is a counter with a set signal and an overflow flag signal.
Parameter
NAME DESCRIPTION DEFAULT max_val_p max value -1 lg_max_val_lp input and output data width `BSG_SAFE_CLOG2(max_val_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT set_i 1 setting port val_i lg_max_val_lp data input port OUTPUT count_o lg_max_val_lp data output port overflow_o 1 data output port Assertion
None
Details & Circuit structure
bsg_counter_set_down¶
Overview
This is a decrement counter with a set.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” init_val_p initial value ‘0 set_and_down_exclusive_p flag bit 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT set_i 1 setting port val_i width_p data input port down_i 1 data input port count_o width_p data output port Assertion
None
Details & Circuit structure
bsg_counter_set_en¶
Overview
This is a decrement counter with a set.
Parameter
NAME DESCRIPTION DEFAULT max_val_p input and output data width “inv” lg_max_val_lp input and output data width `BSG_SAFE_CLOG2(max_val_p) reset_val_p reset value 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT set_i 1 setting port val_i lg_max_val_lp data input port en_i 1 data input port count_o lg_max_val_lp data output port Assertion
None
Details & Circuit structure
bsg_counter_up_down¶
Overview
This is an up-down counter with initial and max values.
Parameter
NAME DESCRIPTION DEFAULT max_val_p max value -1 init_val_p initial value -1 max_step_p input data width -1 step_width_lp input data width `BSG_WIDTH(max_step_p) ptr_width_lp output data width `BSG_WIDTH(max_val_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT up_i step_width_lp data input port down_i step_width_lp data input port OUTPUT count_o ptr_width_lp data output port Assertion
None
Details & Circuit structure
bsg_counter_up_down_variable¶
Overview
This is an up-down counter with initial and max values.
Parameter
NAME DESCRIPTION DEFAULT max_val_p max value -1 init_val_p initial value -1 max_step_p input data width -1 step_width_lp input data width `BSG_WIDTH(max_step_p) ptr_width_lp output data width `BSG_WIDTH(max_val_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT up_i step_width_lp data input port down_i step_width_lp data input port OUTPUT count_o ptr_width_lp data output port Assertion
None
Details & Circuit structure
bsg_counting_leading_zeros¶
Overview
This is a priority encoder that encodes the input reversed first.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port OUTPUT num_zero_o `BSG_SAFE_CLOG2(width_p) data output port Assertion
None
Details & Circuit structure
bsg_cycle_counter¶
Overview
This is a loop counter.
Parameter
NAME DESCRIPTION DEFAULT i_els_p input and output data width -1 o_els_p input and output data width -1 width_p input and output data width -1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port OUTPUT ctr_r_o width_p data output port Assertion
None
Details & Circuit structure
Crossbar Releted Unit¶
bsg_crossbar_control_basic_o_by_i¶
Overview
This module generates the control signals for bsg_router_crossbar_o_by_i.
Parameter
NAME DESCRIPTION DEFAULT i_els_p input and output data width “inv” o_els_p input and output data width “inv” lg_o_els_lp input data width `BSG_SAFE_CLOG2(o_els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT valid_i i_els_p data input port sel_io_i i_els_p*lg_o_els_lp data input port ready_and_i o_els_p data input port OUTPUT yumi_o i_els_p data output port valid_o step_width_lp data output port grants_oi_one_hot_o o_els_p*i_els_p data output port Assertion
None
Details & Circuit structure
bsg_crossbar_o_by_i¶
Overview
This is a benes network implementation.
Parameter
NAME DESCRIPTION DEFAULT i_els_p input and output data width -1 o_els_p input and output data width -1 width_p input and output data width -1
Port
TYPE NAME WIDTH DESCRIPTION INPUT i i_els_p*width_p data input port sel_oi_one_hot_i o_els_p*i_els_p data input port OUTPUT o o_els_p*width_p data output port Assertion
None
Details & Circuit structure
DFF & Latch¶
bsg_dff¶
Overview
This is a DFF without other ports. It is triggered by the positive edge of input clock.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port -1 harden_p use harden IP or not 0 strength_p drive strength 1 Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 input clock INPUT data_i width_p input data OUTPUT data_o width_p output data Assertion
None
Details & Circuit structure
bsg_dff_en¶
Overview
This is a DFF with an enable port. It is triggered by the positive edge of input clock.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port “inv” harden_p use harden IP or not 1 strength_p drive strength 1 Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 input clock INPUT data_i width_p input data en_i 1 enable OUTPUT data_o width_p output data Assertion
None
Details & Circuit structure
bsg_dff_reset¶
Overview
This is a DFF with a reset port. It is triggered by the positive edge of input clock. The reset is synchronous and active high.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port -1 harden_p use harden IP or not 0 reset_val_p initial value of data_o if reset 0 Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 input clock RESET reset_i 1 reset INPUT data_i width_p input data OUTPUT data_o width_p output data Assertion
None
Details & Circuit structure
bsg_dff_reset_en¶
Overview
This is a DFF with reset and enable ports. It is triggered by the positive edge of input clock. The reset is synchronous and active high.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port “inv” harden_p use harden IP or not 0 reset_val_p initial value of output data when reset 0 Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 input clock RESET reset_i 1 reset INPUT data_i width_p input data en_i 1 enable OUTPUT data_o width_p output data Assertion
None
Details & Circuit structure
bsg_dff_negedge_reset¶
Overview
This is a DFF with a reset port. It is triggered by the negative edge of input clock. The reset is synchronous and active high.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port -1 harden_p use harden IP or not 0 Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 input clock RESET reset_i 1 reset INPUT data_i width_p input data OUTPUT data_o width_p output data Assertion
None
Details & Circuit structure
bsg_dff_gatestack¶
Overview
This is a set of DFFs. Each DFF is triggered by the positive edge of the its corresponding bit of i1. There is no reset or enable signals for these DFFs.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port “inv” harden_p use harden IP or not 1 Port
TYPE NAME WIDTH DESCRIPTION INPUT i0 width_p input data i1 width_p data transmission trigger, clocks for each bit of input OUTPUT o width_p output data Assertion
None
Details & Circuit structure
bsg_dff_chain¶
Overview
This is a DFF chain. Input data will be stored num_stages_p times in the DFF chain. All DFFs are triggered by the positive edge of input clock. There are no reset and enable signals in each DFF.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port -1 num_stages_p stage number of DFFs 1 Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 input clock INPUT data_i width_p input data OUTPUT data_o width_p output data Assertion
None
Details & Circuit structure
Input data will be transmitted stage by stage without any stall. If num_stages_p is 0, input data is assigned to output port directly without any registers.
bsg_dff_en_bypass¶
Overview
This is a DFF with a bypass lane. The DFF is triggered by positive edge of the clock. If the DFF is enabled, the output data is changed to be the input data immediately.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port “inv” harden_p use harden IP or not 1 strength_p drive strength 1 Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 input clock INPUT data_i width_p input data en_i 1 enable OUTPUT data_o width_p output data Assertion
None
Details & Circuit structure
When enable is 1, input data is stored into the register and bypassed to the output port at the same time. The module consists of a bsg_dff_en and a bypass lane.
bsg_dff_reset_en_bypass¶
Overview
This is a DFF with a bypass lane and a reset port. The DFF is triggered by positive edge of the clock. If the DFF is enabled, the output data is changed to be the input data immediately. The reset is synchronous and active high.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port “inv” harden_p use harden IP or not 0 reset_val_p initial value of output data when reset 0 Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 input clock RESET reset_i 1 reset INPUT data_i width_p input data en_i 1 enable OUTPUT data_o width_p output data Assertion
None
Details & Circuit structure
When enable is 1, input data is stored into the register and bypassed to the output port at the same time. The module consists of a bsg_dff_reset_en and a bypass lane.
bsg_dff_reset_set_clear¶
Overview
This is a DFF with reset, set and clear ports. It is triggered by positive edge of the clock. The reset is synchronous and active high.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port “inv” clear_over_set_p priorities of clear. If it is 1, clear is prio to set 0 Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 input clock RESET reset_i 1 reset INPUT data_i width_p input data set_i width_p set enable clear_i width_p clear enable OUTPUT data_o width_p output data Assertion
None
Details & Circuit structure
Reset value of the DFF is ‘0. Each bit of the input data has a corresponding set and clear signal. If set_i[i] and clear_i[i] are both 1’b1: a) data_o[i] is 0, when clear_over_set_p is 1. b)data_o[i] is 1, when clear_over_set_p is 0.
bsg_dlatch¶
Overview
This is a dlatch. The clock is active high.
Parameter
NAME DESCRIPTION DEFAULT width_p data width of input and output port “inv” i_know_this_is_a_bad_idea_p show the necessary to instantiate a latch 0 Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 input clock INPUT data_i width_p input data OUTPUT data_o width_p output data Assertion
i_know_this_is_a_bad_idea_p == 0
The default value of i_know_this_is_a_bad_idea_p is 0. If users want to instantiate a latch, it is necessary override i_know_this_is_a_bad_idea_p to show that the instantiation is inevitable and the user know all adverse effects.
Details & Circuit structure
Decode Releted Unit¶
bsg_decode¶
Overview
This unit is a decoder.
Parameter
NAME DESCRIPTION DEFAULT num_out_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT i `BSG_SAFE_CLOG2(num_out_p) data input port OUTPUT o num_out_p data output port Assertion
None
Details & Circuit structure
bsg_decode_with_v¶
Overview
This unit is a decoder and can control whether the output is zero or decoder.
Parameter
NAME DESCRIPTION DEFAULT num_out_p input and output data width -1
Port
TYPE NAME WIDTH DESCRIPTION INPUT i `BSG_SAFE_CLOG2(num_out_p) data input port v_i 1 control port OUTPUT o num_out_p data output port Assertion
None
Details & Circuit structure
bsg_encode_one_hot¶
Overview
This is a one hot encoder.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width 8 o_to_hi_p select signal 1 debug_p debug signal 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT addr_o `BSG_SAFE_CLOG2(width_p) data output port v_o 1 data output port Assertion
None
Details & Circuit structure
bsg_expand_bitmask¶
Overview
This module expands each bit in the input vector by the factor of expand_p.
Parameter
NAME DESCRIPTION DEFAULT in_width_p input and output data width “inv” expand_p select signal “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT i in_width_p data input port OUTPUT o in_width_p*expand_p data output port Assertion
None
Details & Circuit structure
bsg_gray_to_binary¶
Overview
This module converts gray code into binary code.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1
Port
TYPE NAME WIDTH DESCRIPTION INPUT gray_i width_p data input port OUTPUT binary_o width_p data output port Assertion
None
Details & Circuit structure
Edge¶
bsg_edge_detect¶
Overview
This unit produces the fall edge.
Parameter
NAME DESCRIPTION DEFAULT falling_not_rising_p input and output data width 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT sig_i 1 data input port OUTPUT detect_o 1 data output port Assertion
None
Details & Circuit structure
Hash Bank Releted Unit¶
bsg_hash_bank¶
Overview
This module takes a binary address, and a constant number of banks, and then hashes the address across the banks efficiently; outputing the bank #, and the index at that bank.
Parameter
NAME DESCRIPTION DEFAULT banks_p input and output data width “inv” width_p input and output data width “inv” index_width_lp output data width $clog2((2**width_p+banks_p-1)/banks_p) lg_banks_lp output data width `BSG_SAFE_CLOG2(banks_p) debug_lp debug signal 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT bank_o lg_banks_lp data output port index_o index_width_lp data output port Assertion
None
Details & Circuit structure
bsg_hash_bank_reverse¶
Overview
This module is the inverse,taking a bank number and an index, and producing the original address.
Parameter
NAME DESCRIPTION DEFAULT banks_p input and output data width “inv” width_p input and output data width “inv” index_width_lp input data width $clog2((2**width_p+banks_p-1)/banks_p) lg_banks_lp input data width `BSG_SAFE_CLOG2(banks_p) debug_lp debug signal 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT index_i index_width_lp data input port bank_i lg_banks_lp data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
Divider Releted Unit¶
bsg_idiv_iterative¶
Overview
This module is an N-bit integer iterative divider, capable of signed & unsigned division.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width 32
Port
Assertion
None
Details & Circuit structure
bsg_idiv_iterative_controller¶
Overview
The controller of bsg_idiv_iterative module.
Parameter
NAME DESCRIPTION DEFAULT width_p Internal signal width 32
Port
Assertion
None
Details & Circuit structure
Comparator Releted Unit¶
bsg_less_than¶
Overview
This is a two input comparer.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT a_i width_p data input port OUTPUT b_i width_p data output port Assertion
None
Details & Circuit structure
Linear Shifter Releted Uint¶
bsg_level_shift_up_down_sink¶
Overview
This module represents a simple level shifter.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT v0_data_i width_p data input port v1_en_i 1 data input port OUTPUT v1_data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_level_shift_up_down_source¶
Overview
This module represents a simple level shifter.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT v0_data_i width_p data input port v1_en_i 1 data input port OUTPUT v1_data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_lfsr¶
Overview
This module is a LFSR.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 init_val_p initial signal 1 xor_mask_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk 1 clock input port RESET reset_i 1 reset input port INPUT yumi_i 1 data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
Arbitration Releted Unit¶
bsg_locking_arb_fixed¶
Overview
This module is a fixed priority arbitration unit.
Parameter
NAME DESCRIPTION DEFAULT inputs_p input and output data width “inv” lo_to_hi_p select signal 1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk 1 clock input port INPUT ready_i 1 data input port unlock_i 1 data input port reqs_i inputs_p data input port OUTPUT grants_o inputs_p data output port Assertion
None
Details & Circuit structure
Pseudo_Tree Releted Unit¶
bsg_lru_pseudo_tree_backup¶
Overview
This module is a tree pseudo LRU backup finder.
Parameter
NAME DESCRIPTION DEFAULT ways_p input and output data width “inv” lg_ways_lp cyclic variable `BSG_SAFE_CLOG2(ways_p)
Port
TYPE NAME WIDTH DESCRIPTION INPUT disabled_ways_i ways_p data input port OUTPUT modify_mask_o ways_p data output port modify_data_o ways_p data output port Assertion
None
Details & Circuit structure
bsg_lru_pseudo_tree_decode¶
Overview
This module is a Pseudo-Tree-LRU decode unit.
Parameter
NAME DESCRIPTION DEFAULT ways_p output data width “inv” lg_ways_lp input data width `BSG_SAFE_CLOG2(ways_p)
Port
TYPE NAME WIDTH DESCRIPTION INPUT way_id_i lg_ways_lp data input port OUTPUT data_o ways_p data output port mask_o ways_p data output port Assertion
None
Details & Circuit structure
bsg_lru_pseudo_tree_encode¶
Overview
This module is a Pseudo-Tree-LRU encode unit.
Parameter
NAME DESCRIPTION DEFAULT ways_p input data width “inv” lg_ways_lp output data width `BSG_SAFE_CLOG2(ways_p)
Port
TYPE NAME WIDTH DESCRIPTION INPUT lru_i ways_p data input port OUTPUT way_id_o lg_ways_lp data output port Assertion
None
Details & Circuit structure
Selector Releted Unit¶
bsg_mux¶
Overview
This is a selector.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” els_p input data width “inv” harden_p use harden IP or not 0 balanced_p assert signal 0 lg_els_lp input data width `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION INPUT data_i els_p*width_p data input port sel_i lg_els_lp data input port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mux2_gatestack¶
Overview
This is a two-selection selector with width of width_p bits.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT i0 width_p data input port i1 width_p data input port i2 width_p select port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_muxi2_gatestack¶
Overview
This is a two-selection selector with width of width_p bits.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT i0 width_p data input port i1 width_p data input port i2 width_p select port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_mux_bitwise¶
Overview
This module is a two-to-one data selector with width_p bit width.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT data0_i width_p data input port data1_i width_p data input port sel_i width_p sel input port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mux_butterfly¶
Overview
This module has stages of mux which interleaves input data.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” els_p input and output data width. “inv” lg_els_lp input data width. `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION INPUT data1_i els_p*width_p data input port sel_i lg_els_lp sel input port OUTPUT data_o els_p*width_p data output port Assertion
None
Details & Circuit structure
bsg_mux_one_hot¶
Overview
This module is a multi-bit selector with one-hot encoding.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” els_p input and output data width. 1 harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION INPUT data_i els_p*width_p data input port sel_one_hot_i els_p sel input port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mux_segmented¶
Overview
This is a two-selection selector with width of segment_width_p bits.
Parameter
NAME DESCRIPTION DEFAULT data_width_lp input and output data width. segments_p*segment_width_p segments_p number of segments “inv” segment_width_p width of each segment “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT data0_i data_width_lp data input port data1_i data_width_lp data input port sel_i segments_p select port OUTPUT data_o data_width_lp data output port Assertion
None
Details & Circuit structure
pg_tree Releted Unit¶
bsg_pg_tree¶
Overview
This module builds a PG (propagate generate) tree.
Parameter
NAME DESCRIPTION DEFAULT input_width_p input data width “inv” output_width_p ouput data width “inv” nodes_p internal signal width 1 edges_lp internal signal width nodes_p*3 l_edge_p index value 0 r_edge_p index value 0 o_edge_p index value 0 node_TYPE_p index value 0 row_p index value 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT p_i input_width_p data input port g_i input_width_p data input port OUTPUT p_o output_width_p data output port g_o output_width_p data output port Assertion
None
Details & Circuit structure
Popcount Releted Uint¶
bsg_popcount¶
Overview
This module uses a recursive method to reduce the bit width of the input data.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT o log2(width_p+1) data output port Assertion
None
Details & Circuit structure
Reduce Releted Uint¶
bsg_reduce¶
Overview
The function of this module is to perform the reduction.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” xor_p xor operation judgment expression 0 and_p and operation judgment expression 0 or_p or operation judgment expression 0 harden_p use harden IP or not 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT o 1 data output port Assertion
None
Details & Circuit structure
bsg_reduce_segmented¶
Overview
The function of this module is to perform the segment_width_p bit reduction.
Parameter
NAME DESCRIPTION DEFAULT segments_p input and output data width. “inv” xor_p xor operation judgment expression 0 and_p and operation judgment expression 0 or_p or operation judgment expression 0 nor_p nor operation judgment expression 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT i segments_p*segment_width_p data input port OUTPUT o segments_p data output port Assertion
None
Details & Circuit structure
Rotate Shift Releted Unit¶
bsg_rotate_left¶
Overview
This is a left shift.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. -1
Port
TYPE NAME WIDTH DESCRIPTION INPUT data_i width_p data input port rot_i `BSG_SAFE_CLOG2(width_p) data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_rotate_right¶
Overview
This is a right shift.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. -1
Port
TYPE NAME WIDTH DESCRIPTION INPUT data_i width_p data input port rot_i `BSG_SAFE_CLOG2(width_p) data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
scan¶
bsg_scan¶
Overview
This module can encode the input data by selecting different modes.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. -1 xor_p control signal 0 and_p control signal 0 or_p control signal 0 lo_to_hi_p control signal 0 debug_p control signal 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
Cyclically Arbitration¶
bsg_strobe¶
Overview
The function of this module is to cyclically schedule arbitration.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 0
Port
TYPE NAME WIDTH DESCRIPTION INPUT clk_i 1 data input port reset_r_i 1 data input port init_val_r_i width_p data input port OUTPUT strobe_r_o 1 data output port Assertion
None
Details & Circuit structure
Swap Unit¶
bsg_swap¶
Overview
The cell provides three ports(data_i,swap_i,data_o).The function of this module is to exchange the first row and the second row of the input array and output the position.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT data_i width_p data input port swap_i 1 control port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
Edge Detection Unit¶
bsg_thermometer_count¶
Overview
This module encodes and outputs the input data edge detection.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. -1
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_p data input port OUTPUT o $clog2(width_p+1) data output port Assertion
None
Details & Circuit structure
Output Fixed Bit Value Unit¶
bsg_tiehi¶
Overview
The function of this module is to output width_p bit 1.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
bsg_tielo¶
Overview
The function of this module is to output width_p bit 0.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” harden_p use harden IP or not 1
Port
TYPE NAME WIDTH DESCRIPTION OUTPUT o width_p data output port Assertion
None
Details & Circuit structure
Output Switching Position Unit¶
bsg_transpose¶
Overview
The function of this module is to exchange the position of the bit width and the bit width of the input data for the output.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width. “inv” els_p input and output data width. “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT i els_p*width_p data input port OUTPUT o els_p*width_p data output port Assertion
None
Details & Circuit structure
Unconcentrate Uint¶
bsg_unconcentrate_static¶
Overview
The function of this module is to extend the elements of the input vector according to the bit pattern.
Parameter
NAME DESCRIPTION DEFAULT width_p input data width. `BSG_COUNTONES_SYNTH(pattern_els_p) pattern_els_p output data width. “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT i width_1p data input port OUTPUT o $bits(pattern_els_p) data output port Assertion
None
Details & Circuit structure
Reset Unit¶
bsg_wait_after_reset¶
Overview
The function of this module is to wait a certain number of cycles after reset to begin.
Parameter
NAME DESCRIPTION DEFAULT lg_wait_cycles_p register variable bit width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT reset_i 1 clk input port clk_i 1 reset input port OUTPUT ready_r_o 1 data output port Assertion
None
Details & Circuit structure
Wait Cycles Unit¶
bsg_wait_cycles¶
Overview
The function of this module is to wait for several cycles before the circuit starts to work.
Parameter
NAME DESCRIPTION DEFAULT cycles_p circuit intermediate variable bit width “inv”
Port
TYPE NAME WIDTH DESCRIPTION INPUT reset_i 1 clk input port clk_i 1 reset input port activate_i 1 data input port OUTPUT ready_r_o 1 data output port Assertion
None
Details & Circuit structure
