bsg_mem¶
CAM Releted Unit¶
bsg_cam_1r1w¶
Overview
This is an asynchronous read 1r1w content addressable memory module.
Parameter
NAME DESCRIPTION DEFAULT els_p internal signal bit width “inv” tag_width_p input data width “inv” data_width_p input and output data width “inv” repl_scheme_p select signal “lru”
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_nuke_i 1 data input port w_tag_i tag_width_p data input port w_data_i data_width_p data input port r_v_i 1 data input port r_tag_i tag_width_p data input port OUTPUT r_data_o data_width_p data output port r_v_o 1 data output port Assertion
None
Details & Circuit structure
bsg_cam_1r1w_replacement¶
Overview
This module maintains the replacement policy for an array of elements.
Parameter
NAME DESCRIPTION DEFAULT els_p internal signal bit width 2 scheme_p select signal “lru”
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT read_v_i els_p data input port alloc_v_i 1 data input port alloc_empty_i els_p data input port OUTPUT alloc_v_o els_p data output port Assertion
assert (scheme_p == “lru”) else $error(“Only LRU scheme is currently supported”);
Details & Circuit structure
bsg_cam_1r1w_sync¶
Overview
This is synchnronous read 1r1w content addressable memory module.
Parameter
NAME DESCRIPTION DEFAULT els_p internal signal bit width “inv” tag_width_p input data width “lru” data_width_p input and output data width 2 repl_scheme_p select signal “lru”
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_nuke_i 1 data input port w_tag_i tag_width_p data input port w_data_i data_width_p data input port r_v_i 1 data input port r_tag_i tag_width_p data input port OUTPUT r_data_o data_width_p data output port r_v_o 1 data output port Assertion
None
Details & Circuit structure
bsg_cam_1r1w_sync_unmanaged¶
Overview
This is synchnronous read 1r1w content addressable memory module,and each entry has a tag and a data associated with it, and can be independently cleared and set.
Parameter
NAME DESCRIPTION DEFAULT els_p input and output data width “inv” tag_width_p input data width “inv” data_width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i els_p data input port w_set_not_clear_i 1 data input port w_tag_i tag_width_p data input port w_data_i data_width_p data input port r_v_i 1 data input port r_tag_i tag_width_p data input port OUTPUT r_data_o data_width_p data output port r_v_o 1 data output port Assertion
None
Details & Circuit structure
bsg_cam_1r1w_tag_array¶
Overview
This module is made for use in bsg_cams, managing the valids and tags for each entry.
Parameter
NAME DESCRIPTION DEFAULT width_p input data width “inv” els_p input and output data width “inv” multiple_entries_p assert signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i els_p data input port w_set_not_clear_i 1 data input port w_tag_i tag_width_p data input port w_data_i data_width_p data input port r_v_i 1 data input port r_tag_i tag_width_p data input port OUTPUT w_empty_o els_p data output port r_match_o els_p data output port Assertion
assert(multiple_entries_p || reset_i || $countones(r_match_o) <= 1);
Details & Circuit structure
bsg_cam_1r1w_unmanaged¶
Overview
This is an asynchronous read 1r1w content addressable memory module, and Each entry has a tag and a data associated with it, and can be independently cleared and set.
Parameter
NAME DESCRIPTION DEFAULT els_p input and output data width “inv” tag_width_p input data width “inv” data_width_p input and output data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i els_p data input port w_set_not_clear_i 1 data input port w_tag_i tag_width_p data input port w_data_i data_width_p data input port r_v_i 1 data input port r_tag_i tag_width_p data input port OUTPUT w_empty_o els_p data output port r_data_o data_width_p data output port r_v_o els_p data output port Assertion
None
Details & Circuit structure
Asynchronous Mem Releted Unit¶
bsg_mem_1r1w¶
Overview
This module is 1 read-port and 1 write-port ram, and reads are asynchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p internal signal bit width -1 read_write_same_addr_p none 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) harden_p use harden IP or not 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK w_clk_i 1 clock input port RESET w_reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r_v_i 1 data input port r_addr_i addr_width_lp data input port OUTPUT r_data_o width_p data output port Assertion
assert ((w_reset_i === ‘X) || (w_reset_i === 1’b1) || (w_addr_i < els_p)); assert ((w_reset_i === ‘X) || (w_reset_i === 1’b1) || !(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p));
Details & Circuit structure
bsg_mem_1r1w_one_hot¶
Overview
This module is 1 read-port and 1 write-port ram with a onehot address scheme.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK w_clk_i 1 clock input port RESET w_reset_i 1 reset input port INPUT w_v_i els_p data input port w_data_i width_p data input port r_v_i els_p data input port OUTPUT r_data_o width_p data output port Assertion
assert ((w_reset_i === ‘X) || (w_reset_i === 1’b1) || $countones(w_v_i) <= 1); assert ((w_reset_i === ‘X) || (w_reset_i === 1’b1) || $countones(r_v_i) <= 1);
Details & Circuit structure
bsg_mem_1r1w_synth¶
Overview
This module is 1 read-port, 1 write-port ram for synthesizable internal version, and reads are asynchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 read_write_same_addr_p None 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) harden_p use harden IP or not 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK w_clk_i 1 clock input port RESET w_reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i w_data_i data input port r_v_i 1 data input port r_addr_i addr_width_lp data input port OUTPUT r_data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_2r1w¶
Overview
This module is a 2 read-port and 1 write-port ram, and reads are asynchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p select signal -1 read_write_same_addr_p None 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK w_clk_i 1 clock input port RESET w_reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r0_v_i 1 data input port r0_addr_i addr_width_lp data input port r1_v_i 1 data input port r1_addr_i addr_width_lp data input port OUTPUT r0_data_o width_p data output port r1_data_o width_p data output port Assertion
assert (w_addr_i < els_p) assert (!(r0_addr_i == w_addr_i && w_v_i && r0_v_i && !read_write_same_addr_p)) assert (!(r1_addr_i == w_addr_i && w_v_i && r1_v_i && !read_write_same_addr_p))
Details & Circuit structure
bsg_mem_2r1w_synth¶
Overview
This module is a 2 read-port and 1 write-port ram, and reads are asynchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p mem dimensions -1 read_write_same_addr_p None 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK w_clk_i 1 clock input port RESET w_reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r0_v_i 1 data input port r0_addr_i addr_width_lp data input port r1_v_i 1 data input port r1_addr_i addr_width_lp data input port OUTPUT r0_data_o width_p data output port r1_data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_3r1w¶
Overview
This module is a 3 read-port, 1 write-port ram, and reads are asynchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p mem dimensions -1 read_write_same_addr_p None 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK w_clk_i 1 clock input port RESET w_reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r0_v_i 1 data input port r0_addr_i addr_width_lp data input port r1_v_i 1 data input port r1_addr_i addr_width_lp data input port r2_v_i 1 data input port r2_addr_i addr_width_lp data input port OUTPUT r0_data_o width_p data output port r1_data_o width_p data output port r1_data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_3r1w_synth¶
Overview
This module is a 3 read-port, 1 write-port ram, and reads are asynchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p mem dimensions -1 read_write_same_addr_p None 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r0_v_i 1 data input port r0_addr_i addr_width_lp data input port r1_v_i 1 data input port r1_addr_i addr_width_lp data input port r2_v_i 1 data input port r2_addr_i addr_width_lp data input port OUTPUT r0_data_o width_p data output port r1_data_o width_p data output port r2_data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_multiport¶
Overview
This module is a N read-port and M write-port ram, and reads are asynchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p mem dimensions -1 read_write_same_addr_p assertion signal 0 write_write_same_addr_p assertion signal 0 read_ports_p input and output data width “inv” write_ports_p input data width “inv” addr_width_lp input data width `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK w_clk_i 1 clock input port RESET w_reset_i 1 reset input port INPUT w_v_i write_ports_p data input port w_addr_i write_ports_p*addr_width_lp data input port w_data_i write_ports_p*width_p data input port r_v_i read_ports_p data input port r_addr_i read_ports_p*addr_width_lp data input port OUTPUT r0_data_o read_ports_p*width_p data output port Assertion
assert (w_addr_i[i] < els_p); assert (~(w_addr_i[i] == r_addr_i[j] && w_v_i[i] && r_v_i[j] && !read_write_same_addr_p)); assert (~(w_addr_i[i] == w_addr_i[j] && w_v_i[i] && w_v_i[j] && !write_write_same_addr_p));
Details & Circuit structure
Synchronous Mem Releted Unit¶
bsg_mem_1r1w_sync¶
Overview
This module is 1 read-port and 1 write-port ram, and reads are synchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 read_write_same_addr_p input data width 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) harden_p use harden IP or not 0 disable_collision_warning_p detection signal 1 enable_clock_gating_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r_v_i 1 data input port r_addr_i addr_width_lp data input port OUTPUT r_data_o width_p data output port Assertion
assert ((reset_i === ‘X) || (reset_i === 1’b1) || (w_addr_i < els_p)); assert ((reset_i === ‘X) || (reset_i === 1’b1) || ~(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p && !disable_collision_warning_p));
Details & Circuit structure
bsg_mem_1r1w_sync_mask_write_bit¶
Overview
This module is 1 read-port and 1 write-port ram with mask, and reads are synchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 read_write_same_addr_p input data width 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) harden_p use harden IP or not 0 disable_collision_warning_p detection signal 1 enable_clock_gating_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_mask_i width_p data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r_v_i 1 data input port r_addr_i addr_width_lp data input port OUTPUT r_data_o width_p data output port Assertion
assert ((reset_i === ‘X) || (reset_i === 1’b1) || (w_addr_i < els_p)); assert ((reset_i === ‘X) || (reset_i === 1’b1) || (~(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p && !disable_collision_warning_p)));
Details & Circuit structure
bsg_mem_1r1w_sync_mask_write_bit_synth¶
Overview
This module is 1 read-port and 1 write-port ram with mask, and reads are synchronous. This is synth version.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 read_write_same_addr_p input data width 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) harden_p use harden IP or not 0 disable_collision_warning_p detection signal 1
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_mask_i width_p data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r_v_i 1 data input port r_addr_i addr_width_lp data input port OUTPUT r_data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_1r1w_sync_mask_write_var¶
Overview
This module is 1 read-port and 1 write-port ram, and reads are synchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 els_p input data width -1 chunk_size_lp cycle range width_p / mask_width_p addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) harden_p use harden IP or not 0 read_write_same_addr_p detection signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_mask_i width_p data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r_v_i 1 data input port r_addr_i addr_width_lp data input port OUTPUT r_data_o width_p data output port Assertion
assert ((reset_i === ‘X) || (reset_i === 1’b1) || (w_addr_i < els_p)); assert ((reset_i === ‘X) || (reset_i === 1’b1) || ~(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p && !disable_collision_warning_p));
Details & Circuit structure
bsg_mem_1rw_sync_synth¶
Overview
This module is synchronous 1-port ram, and only one read or one write may be done per cycle.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 latch_last_read_p select signal 0 addr_width_lp cycle range `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT v_i 1 data input port data_i width_p data input port addr_i addr_width_lp data input port w_i 1 data input port OUTPUT data_o width_p data output port Assertion
assert ( (v_i !== 1’b1) || (reset_i === ‘X) || (reset_i === 1’b1) || (addr_i < els_p));
Details & Circuit structure
bsg_mem_1rw_sync¶
Overview
This module is synchronous 1-port ram, and only one read or one write may be done per cycle.
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port addr_i addr_width_lp data input port v_i 1 data input port w_i 1 data input port OUTPUT data_o width_p data output port
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 latch_last_read_p select signal 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) enable_clock_gating_p select signal 0
Assertion
assert ( (v_i !== 1’b1) || (reset_i === ‘X) || (reset_i === 1’b1) || (addr_i < els_p));
Details & Circuit structure
bsg_mem_1rw_sync_banked¶
Overview
This module can be used for breaking a big SRAM block intosmaller blocks.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” els_p input data width “inv” latch_last_read_p select signal 0 num_width_bank_p cycle range 1 num_depth_bank_p internal signal bit width 1 addr_width_lp input and output data width `BSG_SAFE_CLOG2(els_p) bank_depth_lp input data width els_p/num_depth_bank_p bank_addr_width_lp internal signal bit width `BSG_SAFE_CLOG2(bank_depth_lp) depth_bank_idx_width_lp internal signal bit width `BSG_SAFE_CLOG2(num_depth_bank_p) bank_width_lp select signal width_p/num_width_bank_p
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port addr_i addr_width_lp data input port v_i 1 data input port w_i 1 data input port OUTPUT data_o width_p data output port Assertion
assert(els_p % num_depth_bank_p == 0); assert(width_p % num_width_bank_p == 0);
Details & Circuit structure
bsg_mem_1rw_sync_mask_write_bit¶
Overview
This module is a synchronous 1-port ram with mask, and only one read or one write may be done per cycle.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 latch_last_read_p select signal 0 enable_clock_gating_p select signal 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port addr_i addr_width_lp data input port v_i 1 data input port w_mask_i width_p data input port w_i 1 data input port OUTPUT data_o width_p data output port Assertion
assert ((reset_i === ‘X) || (reset_i === 1’b1) || (addr_i < els_p));
Details & Circuit structure
bsg_mem_1rw_sync_mask_write_bit_banked¶
Overview
This module can be used for breaking a big SRAM block into smaller blocks.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” els_p input data width “inv” latch_last_read_p select signal 0 num_width_bank_p cycle range 1 num_depth_bank_p internal signal bit width 1 addr_width_lp input and output data width `BSG_SAFE_CLOG2(els_p) bank_depth_lp input data width els_p/num_depth_bank_p bank_addr_width_lp internal signal bit width `BSG_SAFE_CLOG2(bank_depth_lp) depth_bank_idx_width_lp internal signal bit width `BSG_SAFE_CLOG2(num_depth_bank_p) bank_width_lp select signal width_p/num_width_bank_p
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port addr_i addr_width_lp data input port v_i 1 data input port w_mask_i width_p data input port w_i 1 data input port OUTPUT data_o width_p data output port Assertion
assert(els_p % num_depth_bank_p == 0); assert(width_p % num_width_bank_p == 0);
Details & Circuit structure
bsg_mem_1rw_sync_mask_write_bit_synth¶
Overview
This module is synchronous 1-port ram, and only one read or one write may be done per cycle.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p internal signal bit width -1 latch_last_read_p select signal 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port addr_i addr_width_lp data input port v_i 1 data input port w_mask_i width_p data input port w_i 1 data input port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_1rw_sync_mask_write_byte¶
Overview
This module is synchronous 1-port ram with mask, and only one read or one write may be done per cycle. For each bit sey in the mask, a byte is written.
Parameter
NAME DESCRIPTION DEFAULT els_p input data width -1 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) data_width_p input and output data width -1 latch_last_read_p select signal 0 write_mask_width_lp input data width data_width_p>>3 enable_clock_gating_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i data_width_p data input port addr_i addr_width_lp data input port v_i 1 data input port w_mask_i write_mask_width_lp data input port w_i 1 data input port OUTPUT data_o data_width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_1rw_sync_mask_write_byte_banked¶
Overview
This module is synchronous 1-port ram with mask, and only one read or one write may be done per cycle. For each bit sey in the mask, a byte is written.
Parameter
NAME DESCRIPTION DEFAULT data_width_p input and output data width “inv” els_p input data width “inv” latch_last_read_p input data width 0 write_mask_width_lp input data width data_width_p>>3 num_width_bank_p cycle range 1 num_depth_bank_p internal signal bit width 1 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) bank_depth_lp input data width els_p/num_depth_bank_p bank_addr_width_lp internal signal bit width `BSG_SAFE_CLOG2(bank_depth_lp) depth_bank_idx_width_lp internal signal bit width `BSG_SAFE_CLOG2(num_depth_bank_p) bank_width_lp select signal data_width_p/num_width_bank_p bank_mask_width_lp signal bit wide range bank_width_lp>>3
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i data_width_p data input port addr_i addr_width_lp data input port v_i 1 data input port w_mask_i write_mask_width_lp data input port w_i 1 data input port OUTPUT data_o data_width_p data output port Assertion
assert (data_width_p % 8 == 0); assert(els_p % num_depth_bank_p == 0); assert(data_width_p % num_width_bank_p == 0);
Details & Circuit structure
bsg_mem_1rw_sync_mask_write_byte_synth¶
Overview
This module is synchronous 1-port ram with mask for synthesizable internal version, and only one read or one write may be done per cycle. For each bit sey in the mask, a byte is written.
Parameter
NAME DESCRIPTION DEFAULT els_p input data width -1 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) latch_last_read_p select signal 0 data_width_p input data width -1 write_mask_width_lp input data width data_width_p>>3
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i data_width_p data input port addr_i addr_width_lp data input port v_i 1 data input port write_mask_i write_mask_width_lp data input port w_i 1 data input port OUTPUT data_o data_width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_1rw_sync_mask_write_var¶
Overview
This module is a synchronous 1-port ram with mask, and only one read or one write may be done per cycle.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 mask_width_p input data width -1 els_p select signal -1 chunk_size_lp cycle range width_p / mask_width_p addr_width_lp input data width `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port addr_i addr_width_lp data input port v_i 1 data input port w_mask_i width_p data input port w_i 1 data input port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_2r1w_sync¶
Overview
This module is a 2 read-port and 1 write-port ram, and reads are synchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 read_write_same_addr_p None 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) harden_p use harden IP or not 0 enable_clock_gating_p select signal `BSG_SAFE_CLOG2(els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r0_v_i 1 data input port r0_addr_i addr_width_lp data input port r1_v_i 1 data input port r1_addr_i addr_width_lp data input port OUTPUT r0_data_o width_p data output port r1_data_o width_p data output port Assertion
assert (w_addr_i < els_p) assert (~(r0_addr_i == w_addr_i && w_v_i && r0_v_i && !read_write_same_addr_p)) assert (~(r1_addr_i == w_addr_i && w_v_i && r1_v_i && !read_write_same_addr_p))
Details & Circuit structure
bsg_mem_2r1w_sync_synth¶
Overview
This module is a 2 read-port and 1 write-port ram, and reads are synchronous.This is synthesize version.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p input data width -1 read_write_same_addr_p None 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) harden_p use harden IP or not 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r0_v_i 1 data input port r0_addr_i addr_width_lp data input port r1_v_i 1 data input port r1_addr_i addr_width_lp data input port OUTPUT r0_data_o width_p data output port r1_data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_3r1w_sync¶
Overview
This module is a 3 read-port, 1 write-port ram, and reads are synchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p mem dimensions -1 read_write_same_addr_p None 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) harden_p use harden IP or not 0 enable_clock_gating_p select signal 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r0_v_i 1 data input port r0_addr_i addr_width_lp data input port r1_v_i 1 data input port r1_addr_i addr_width_lp data input port r2_v_i 1 data input port r2_addr_i addr_width_lp data input port OUTPUT r0_data_o width_p data output port r1_data_o width_p data output port r2_data_o width_p data output port Assertion
assert (w_addr_i < els_p); assert (~(r0_addr_i == w_addr_i && r0_v_i && !read_write_same_addr_p)); assert (~(r1_addr_i == w_addr_i && r1_v_i && !read_write_same_addr_p)); assert (~(r2_addr_i == w_addr_i && r2_v_i && !read_write_same_addr_p));
Details & Circuit structure
bsg_mem_3r1w_sync_synth¶
Overview
This module is a 3 read-port, 1 write-port ram, and reads are synchronous.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width -1 els_p mem dimensions -1 read_write_same_addr_p None 0 addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) harden_p use harden IP or not 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port r0_v_i 1 data input port r0_addr_i addr_width_lp data input port r1_v_i 1 data input port r1_addr_i addr_width_lp data input port r2_v_i 1 data input port r2_addr_i addr_width_lp data input port OUTPUT r0_data_o width_p data output port r1_data_o width_p data output port r2_data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_mem_banked_crossbar¶
Overview
This module is a bank mem banked crossbar.
Parameter
NAME DESCRIPTION DEFAULT i_els_p input and output data width -1 o_els_p input and output data width -1 rr_lo_hi_p select signal “inv” lg_o_els_lp input data width `BSG_SAFE_CLOG2(o_els_p)
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port reverse_pr_i 1 data input port valid_i i_els_p data input port sel_io_i i_els_p*lg_o_els_lp data input port ready_i o_els_p data input port OUTPUT yumi_o i_els_p data output port valid_o o_els_p data output port grants_oi_one_hot_o o_els_p*i_els_p data output port Assertion
None
Details & Circuit structure
bsg_nonsynth_mem_1r1w_sync_dma¶
Overview
This module is synchronous 1 read-port and 1 write-port mem.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” els_p input data width -1 id_p input and output data width “inv” data_width_in_bytes_lp cycle range width_p>>3 write_mask_width_lp input data width data_width_in_bytes_lp addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) byte_offset_width_lp internal signal bit wide range `BSG_SAFE_CLOG2(data_width_in_bytes_lp) init_mem_p chandle parameter 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT r_v_i 1 data input port r_addr_i addr_width_lp data input port w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma¶
Overview
This module is synchronous 1 read-port and 1 write-port mem with mask.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” els_p input data width -1 id_p input and output data width “inv” data_width_in_bytes_lp cycle range width_p>>3 write_mask_width_lp input data width data_width_in_bytes_lp addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) byte_offset_width_lp internal signal bit wide range `BSG_SAFE_CLOG2(data_width_in_bytes_lp) init_mem_p chandle parameter 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT r_v_i 1 data input port r_addr_i addr_width_lp data input port w_v_i 1 data input port w_addr_i addr_width_lp data input port w_data_i width_p data input port w_mask_i write_mask_width_lp data input port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_nonsynth_mem_1rw_sync_assoc¶
Overview
This module is for simulating arbitrarily large memories.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” addr_width_p input data width “inv”
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port addr_i addr_width_p data input port v_i 1 data input port w_i 1 data input port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
bsg_nonsynth_mem_1rw_sync_mask_write_byte_assoc¶
Overview
This module is for simulating arbitrarily large memories with mask.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” addr_width_p input data width “inv” write_mask_width_lp input data width data_width_p>>3
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port addr_i addr_width_p data input port v_i 1 data input port w_i 1 data input port write_mask_i write_mask_width_lp data input port OUTPUT data_o data_width_p data output port Assertion
None
Details & Circuit structure
bsg_nonsynth_mem_1rw_sync_mask_write_byte_dma¶
Overview
This module implements synchronous byte mem with mask.
Parameter
NAME DESCRIPTION DEFAULT width_p input and output data width “inv” els_p input data width -1 id_p input and output data width “inv” data_width_in_bytes_lp cycle range width_p>>3 write_mask_width_lp input data width data_width_in_bytes_lp addr_width_lp input data width `BSG_SAFE_CLOG2(els_p) byte_offset_width_lp internal signal bit wide range `BSG_SAFE_CLOG2(data_width_in_bytes_lp) init_mem_p chandle parameter 0
Port
TYPE NAME WIDTH DESCRIPTION CLOCK clk_i 1 clock input port RESET reset_i 1 reset input port INPUT data_i width_p data input port addr_i addr_width_lp data input port v_i 1 data input port w_i 1 data input port w_mask_i write_mask_width_lp data input port OUTPUT data_o width_p data output port Assertion
None
Details & Circuit structure
